M25P05 ,NOT FOR NEW DESIGNLogic DiagramVCCD QCS M25P05WHOLDVSSAI04037Table 1. Signal NamesC Serial ClockD Serial Data InputQ ..
M25P05AV ,512 KBIT, LOW VOLTAGE, SERIAL FLASH MEMORY WITH 25 MHZ SPI BUS INTERFACELogic DiagramVCCD QCS M25P05-AWHOLDVSSAI05757Table 1. Signal NamesC Serial ClockD Serial Data Input ..
M25P05-AVDW6TP , 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
M25P05-AVDW6TP , 512 Kbit, serial Flash memory, 50 MHz SPI bus interface
M25P05AVMN6 ,512 Kbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus InterfaceM25P05-A512 Kbit, Low Voltage, Serial Flash MemoryWith 50MHz SPI Bus Interface
M25P05-AVMN6 ,512 Kbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus InterfaceFEATURES SUMMARY■ 512 Kbit of Flash Memory Figure 1. Packages■ Page Program (up to 256 Bytes) in 1. ..
M38185ME-193FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-259FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-277FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38197EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38197EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38199MF-065FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M25P05
NOT FOR NEW DESIGN
1/32
NOT FOR NEW DESIGNFebruary 2002
M25P05512 Kbit, Low Voltage, Serial Flash Memory
With 20 MHz SPI Bus Interface
FEATURES SUMMARYThis device is now designated as “Not for New De-
sign”. Please use the M25P05-A in all future de-
signs (as described in application note AN1511). 512 Kbit of Flash Memory Page Program (up to 128 Bytes) in 3 ms
(typical) Sector Erase (256 Kbit) in 1 s (typical) Bulk Erase (512 Kbit) in 2 s (typical) 2.7 V to 3.6 V Single Supply Voltage SPI Bus Compatible Serial Interface 20 MHz Clock Rate (maximum) Deep Power-down Mode 1 μA (typical) Electronic Signature More than 100,000 Erase/Program Cycles per
Sector More than 20 Year Data Retention
Figure 1. Packages
M25P05
SUMMARY DESCRIPTION
Figure 3. SO Connections
Table 1. Signal Names
3/32
M25P05
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip Select (S) Low enables the device, placing it
in the active power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to freeze the size of the area of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP1
and BP0 bits of the Status Register).
M25P05
SPI MODESThese devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes: CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5, is the clock polarity when the bus mas-
ter is in Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1)
5/32
M25P05
OPERATING FEATURES
Page ProgrammingTo program one data byte, two instructions are re-
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP)
instruction allows up to 128 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
Sector Erase and Bulk EraseThe Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all
1s (FFh). This can be achieved either a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction.
Polling During a Write, Program or Erase CycleA further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) bit is provided in the Status Regis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
Active Power, Stand-by Power and Deep
Power-Down ModesWhen Chip Select (S) is Low, the device is en-
abled, and in the Active Power mode.
When Chip Select (S) is High, the device is dis-
abled, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write Status Register). The device then
goes in to the Stand-by Power mode. The device
consumption drops to ICC1.
The Deep Power-down mode is entered when the
specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device
consumption drops further to ICC2. The device re-
mains in this mode until another specific instruc-
tion (the Release from Deep Power-down Mode
and Read Electronic Signature (RES) instruction)
is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
device from inadvertant Write, Program or Erase
instructions.
Status RegisterThe Status Register contains a number of status
and control bits, as shown in Table 5, that can be
read or set (as appropriate) by specific instruc-
tions.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
M25P05
Table 2. Protected Area Sizes
Protection ModesThe environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25P05 boasts the
following data protection mechanisms: Power-On Reset and an internal timer (tPUW)
can provide protection against inadvertant
changes while the power supply is outside the
operating specification. Program, Erase and Write Status Register
instructions are checked that they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution. All instructions that modify data must be
preceded by a Write Enable (WREN) instruction
to set the Write Enable Latch (WEL) bit . This bit
is returned to its reset state by the following
events: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction
completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only. This
is the Software Protected Mode (SPM). The Write Protect (W) signal, in co-operation
with the Status Register Write Disable (SRWD)
bit, allows the Block Protect (BP1, BP0) bits and
Status Register Write Disable (SRWD) bit to be
write-protected. This is the Hardware Protected
Mode (HPM). In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one particular
instruction (the Release from Deep Power-
down instruction).
7/32
M25P05
Hold ConditionThe Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low (as shown in Fig-
ure 6).
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts
when Serial Clock (C) next goes Low. Similarly, if
the rising edge does not coincide with Serial Clock
(C) being Low, the Hold condition ends when Se-
rial Clock (C) next goes Low. (This is shown in Fig-
ure 6).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of
the internal logic remains unchanged from the mo-
ment of entering the Hold condition.
If Chip Select (S) goes High while the device is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back
to the Hold condition.
M25P05
MEMORY ORGANIZATIONThe memory is organized as: 65536 bytes (8 bits each) 2 sectors (256 Kbits, 32768 bytes each) 512 pages (128 bytes each).
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
Table 3. Memory Organization
9/32
M25P05
INSTRUCTIONSAll instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4.
Depending on the instruction, the one-byte in-
struction code is followed by address bytes, or by
data bytes, or by both or none. Chip Select (S)
must be driven High after the last bit of the instruc-
tion sequence has been shifted in.
At the end of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) or Write Status Register
(WRSR) instruction, Chip Select (S) must be driv-
en High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number
of clock pulses after Chip Select (S) being driven
Low is an exact multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
Table 4. Instruction Set
M25P05
Figure 8. Write Enable (WREN) Sequence
Write Enable (WREN)The Write Enable (WREN) instruction (Figure 8)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 9. Write Disable (WRDI) Sequence
Write Disable (WRDI)The Write Disable (WRDI) instruction (Figure 9)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions: Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction com-
pletion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
11/32
M25P05
Figure 10. Read Status Register (RDSR) Sequence
Read Status Register (RDSR)The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 10.
Table 5. Status Register FormatNote:1. SRWD, BP1 and BP0 are non-volatile read and write bits. WEL and WIP are volatile read-only bits (WEL is set and
reset by specific instructions; WIP is automatically set
and reset by the internal logic of the device).
The status and control bits of the Status Register
are as follows:
WIP bit. The Write In Process (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software protected against Program and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. When both of
the Block Protect (BP1, BP0) bits are set to 1, the
whole memory is protected against Page Program
(PP) and Sector Erase (SE) instructions. The Bulk
Erase (BE) instruction is executed if, and only if,
both Block Protect (BP1, BP0) bits are 0. This is
summarized in Table 2. The Block Protect (BP1,
BP0) bits can be written provided that the Hard-
ware Protected mode has not been set.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile
bits of the Status Register (SRWD, BP1, BP0) be-
come read-only bits and the Write Status Register
(WRSR) instruction is no longer accepted for exe-
cution.
b7 b0
M25P05
Figure 11. Write Status Register (WRSR) Sequence
Write Status Register (WRSR)The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S) is driv-
en High, the self-timed Write Status Register cycle
(whose duration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complet-
ed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2. The Write Status Register (WRSR) in-
struction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in ac-
cordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
13/32
M25P05
Table 6. Protection ModesNote:1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2.
The protection features of the device are summa-
rized in Table 6.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W): If Write Protect (W) is driven High, it is possible
to write to the Status Register provided that the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not pos-
sible to write to the Status Register even if the
Write Enable Latch (WEL) bit has previously
been set by a Write Enable (WREN) instruction.
(Attempts to write to the Status Register are re-
jected, and are not accepted for execution). As
a consequence, all the data bytes in the memo-
ry area that are software protected (SPM) by the
Block Protect (BP1, BP0) bits of the Status Reg-
ister, are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low or by driving Write Protect (W) Low after setting
the Status Register Write Disable (SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
M25P05
Figure 12. Read Data Bytes (READ) SequenceNote:1. Address bits A23 to A16 must be set to 00h.
Read Data Bytes (READ)The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
There is no address roll-over; when the highest
address (0FFFFh) is reached, the instruction
should be terminated.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
15/32
M25P05
Figure 13. Page Program (PP) SequenceNote:1. Address bits A23 to A16 must be set to 00h.
Page Program (PP)The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes (of which the
most significant byte, A23-A16, must be 00h) and
at least one data byte on Serial Data Input (D). If
the 7 least significant address bits (A6-A0) are not
all zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are pro-
grammed from the start address of the same page
(the one whose 7 least significant address bits
(A6-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 13.
If more than 128 bytes are sent to the device, pre-
viously latched data are discarded and the last 128
data bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 128 Data
bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other bytes of the same
page.
Chip Select (S) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. When the cycle is completed, the Write
Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP0, BP1)
bits (see Table 2) is not executed.
M25P05
Figure 14. Sector Erase (SE) SequenceNote:1. Address bits A23 to A16 must be set to 00h.
Sector Erase (SE)The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Erase cy-
cle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP)
bit. The Write In Progress (WIP) bit is 1 during the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL)
bit is reset.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see Table 2) is not executed.
