M24C64-WMN3TP/P ,Automotive 64 Kbit serial I2C bus EEPROMFeatures2■ Compatible with all I C bus modes:– 400 kHz Fast mode– 100 kHz Standard mode■ Memory arr ..
M24C64WMN6 ,64Kbit and 32Kbit Serial IC Bus EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Power On Reset: VCC Lock-Out Write Prot ..
M24C64-WMN6 ,64Kbit and 32Kbit Serial IC Bus EEPROMFEATURES SUMMARY2■ Two-Wire I C Serial Interface Figure 1. PackagesSupports 400kHz Protocol■ Single ..
M24C64WMN6P ,64Kbit and 32Kbit Serial IC Bus EEPROMAbsolute Maximum Ratings . . . . . . . 14DC AND AC PARAMETERS . 15Table 8. Operating Cond ..
M24C64-WMN6P ,64Kbit and 32Kbit Serial IC Bus EEPROMBlock Diagram . . 7DEVICE OPERATION . . . . . . . 8Start Condition . 8Stop Con ..
M24C64WMN6T ,64/32 Kbit Serial IC Bus EEPROMM24C64M24C3264Kbit and 32Kbit Serial I²C Bus EEPROM
M38184EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184M8-132FP-E1 , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184MA-179FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-101FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-193FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M24C64-WMN3TP/P
Automotive 64 Kbit serial I2C bus EEPROM
February 2012 Doc ID 022639 Rev 1 1/29
M24C64-125Automotive 64-Kbit serial I²C bus EEPROM
Features Compatible with all I2 C bus modes: 400 kHz Fast mode 100 kHz Standard mode Memory array: 64 Kbit (8 Kbytes) of EEPROM Page size: 32 bytes Write Byte Write within 5 ms Page Write within 5 ms Single supply voltage: 2.5 V to 5.5V Operating temperature range: from -40 °C up
to +125 °C Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 1 million Write cycles More than 40-year data retention Packages RoHS compliant and halogen-free
(ECOPACK®)
Contents M24C64-1252/29 Doc ID 022639 Rev 1
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.3 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.4 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
M24C64-125 ContentsDoc ID 022639 Rev 1 3/29
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
List of tables M24C64-125
4/29 Doc ID 022639 Rev 1
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. DC characteristics (M24C64-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 25
Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 26
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M24C64-125 List of figures
Doc ID 022639 Rev 1 5/29
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. I2 C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2 C bus at maximum frequency fC = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 26
Description M24C64-125
6/29 Doc ID 022639 Rev 1
1 Description
The M24C64 is a 64-Kbit I2 C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 8 K × 8 bits.
This I2 C EEPROM can operate with a supply voltage from 2.5 V up to 5.5 V over an ambient
temperature range of -40 °C / 125 °C.
The device is compliant with the Automotive standard AEC-Q100 grade 1.
Figure 1. Logic diagram
Figure 2. 8-pin package connections See Section 9: Package mechanical data for package dimensions, and how to identify pin1.
Table 1. Signal names
M24C64-125 Signal description
Doc ID 022639 Rev 1 7/29
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 11 indicates how to calculate the value of the pull-up resistor). In most
applications, though, this method of synchronization is not employed, and so the pull-up
resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 11 indicates how
to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs
are read as low (0).
Figure 3. Device select code
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
Signal description M24C64-125
8/29 Doc ID 022639 Rev 1
2.5 V SS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (V CC)
2.6.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10
nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that is there is no internal
write cycle in progress).
M24C64-125 Memory organization
Doc ID 022639 Rev 1 9/29
3 Memory organization
The memory is organized as shown in Figure4.
Figure 4. Block diagram
Device operation M24C64-125
10/29 Doc ID 022639 Rev 1
4 Device operation
The device supports the I2 C protocol. This is summarized in Figure 5. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
2
M24C64-125 Device operation
Doc ID 022639 Rev 1 11/29
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.5 Memory addressing o start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier 1010b, and a 3-bit Chip
Enable address (E2, E1, E0). A device select code handling a value other than 1010b is not
acknowledged by the device.
Table 2. Device select code The most significant bit, b7, is sent first. E0, E1 and E2 are compared against the respective external pins on the memory device.
Device operation M24C64-125
12/29 Doc ID 022639 Rev 1
Up to eight memory devices can be connected on a single I2 C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 3. Operating modes X = VIH or VIL.
M24C64-125 Instructions
Doc ID 022639 Rev 1 13/29
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 6, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
Each byte location is defined by several address bits inside two address bytes. If the
address bits are less than 16, the most significant bits (A15 and lower) are Don't Care. The
most significant address byte (Table 4) is sent first, followed by the least significant address
byte (Table5).
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure7.
Table 4. Most significant address byte
Table 5. Least significant address byte
Instructions M24C64-125
14/29 Doc ID 022639 Rev 1
5.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure6.
Figure 6. Write mode sequences with WC = 0 (data write enabled)
M24C64-125 Instructions
Doc ID 022639 Rev 1 15/29
5.1.2 Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, b12-b5, are the same. If more bytes are sent than will fit up to the end
of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the
page are overwritten.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 7. After each byte is transferred, the internal byte address counter is
incremented. The transfer is terminated by the bus master generating a Stop condition.
Figure 7. Write mode sequences with WC = 1 (data write inhibited)
