M24C64-FDW6TP ,64 Kbit serial I2C bus EEPROMFeatures2• Compatible with all I C bus modes:–1 MHz– 400 kHz– 100 kHzTSSOP8 (DW)• Memory array:169 ..
M24C64-MN6 ,64Kbit and 32Kbit Serial IC Bus EEPROMBlock Diagram . . 7DEVICE OPERATION . . . . . . . 8Start Condition . 8Stop Con ..
M24C64-MN6T ,64Kbit and 32Kbit Serial IC Bus EEPROMM24C64M24C3264Kbit and 32Kbit Serial I²C Bus EEPROM
M24C64-MN6TP ,64Kbit and 32Kbit Serial IC Bus EEPROMFEATURES SUMMARY . . . . . 1Table 1. Product List . . . . 1Figure 1. Packages . ..
M24C64MW6T ,64/32 Kbit Serial IC Bus EEPROMLogic Diagram SCL Serial ClockWC Write ControlVCCV Supply VoltageCCV GroundSS3Power On Reset: V Loc ..
M24C64-RDW6T ,64Kbit and 32Kbit Serial IC Bus EEPROMLogic Diagram . . 4Table 2. Signal Names . . 4Power On Reset: VCC Lock-Out Write Prot ..
M38184EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184EAFP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184M8-132FP-E1 , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38184MA-179FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-101FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38185ME-193FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M24C64-FDW6TP
64-Kbit Serial I2C bus EEPROM
November 2014 DocID16891 Rev 30 1/45
M24C64-W M24C64-R M24C64-F
M24C64-DF64-Kbit serial I²C bus EEPROM
Datasheet - production data
Features Compatible with all I2 C bus modes:
–1 MHz 400 kHz 100 kHz Memory array: 64 Kbit (8 Kbytes) of EEPROM Page size: 32 bytes Additional Write lockable page
(M24C64-D order codes) Single supply voltage: 1.7 V to 5.5 V over –40 °C / +85 °C 1.6 V to 5.5 V over 0 °C / +85 °C Write: Byte Write within 5 ms Page Write within 5 ms Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-year data retention
Packages PDIP8 ECOPACK1® SO8 ECOPACK2® TSSOP8 ECOPACK2® UFDFPN8 ECOPACK2® WLCSP ECOPACK2® UFDFPN5 ECOPACK2®
Contents M24C64-W M24C64-R M24C64-F 2/45 DocID16891 Rev 30
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 17
5.1.4 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 17
5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17
5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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M24C64-W M24C64-R M24C64-F 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.3 Read Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 20
5.4 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of tables M24C64-W M24C64-R M24C64-F
4/45 DocID16891 Rev 30
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. DC characteristics (M24C64-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. DC characteristics (M24C64-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. DC characteristics (M24C64-F, M24C64-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 17. 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 18. UFDFPN5 (MLP5) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 34
Table 20. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 35
Table 21. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 36
Table 22. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23. WLCSP 5-bump wafer-length chip-scale package mechanical data
(M24C64-FCS6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 24. Thin WLCSP 8-bump wafer-length chip-scale package mechanical data
(M24C64-DFCT6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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M24C64-W M24C64-R M24C64-F
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. UFDFPN5 package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. 5-bump WLCSP connections (M24C64-FCS6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. 8-bump thin WLCSP connections (M24C64-DFCT6TP/K). . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. I2 C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Maximum Rbus value versus bus parasitic capacitance Cbus) for
an I2 C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. UFDFPN5 (MLP5) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 35
Figure 20. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 36
Figure 21. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. WLCSP 5-bump wafer-length chip-scale package outline
(M24C64-FCS6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 23. Thin WLCSP 8-bump wafer-length chip-scale package outline
(M24C64-DFCT6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Description M24C64-W M24C64-R M24C64-F
6/45 DocID16891 Rev 30
1 Description
The M24C64 is a 64-Kbit I2 C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 8 K × 8 bits.
Over an ambient temperature range of -40 °C / +85 °C, the M24C64-W can operate with a
supply voltage from 2.5 V to 5.5 V, the M24C64-R can operate with a supply voltage from
1.8 V to 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from
1.7 V to 5.5 V ( the M24C64-F can also operate down to 1.6 V, under some restricting
conditions).
The M24C64-D offers an additional page, named the Identification Page (32 bytes). The
Identification Page can be used to store sensitive application parameters which can be
(later) permanently locked in Read-only mode.
Figure 1. Logic diagram
Table 1. Signal names
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Figure 2. 8-pin package connections, top view See Section 9: Package mechanical data for package dimensions, and how to identify pin 1
Figure 3. UFDFPN5 package connections
Note: Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for
further explanations.
Note: Inputs E2, E1, E0 are internally connected to (001). Please refer to Section 2.3 for further
explanations.
Signal description M24C64-W M24C64-R M24C64-F
8/45 DocID16891 Rev 30
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 14
indicates how to calculate the value of the pull-up resistor).
2.3 Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must
be tied to VCC or VSS, as shown in Figure 6. When not connected (left floating), these inputs
are read as low (0). For the 5-balls WLCSP package (see Figure 3), the (E2,E1,E0) inputs
are internally connected to (0,0,1).
Figure 6. Chip enable inputs connection
2.4 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
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2.5 V SS (ground)
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (V CC)
2.6.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset
threshold voltage, the device stops responding to any instruction sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Memory organization M24C64-W M24C64-R M24C64-F
10/45 DocID16891 Rev 30
3 Memory organization
The memory is organized as shown below.
Figure 7. Block diagram
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4 Device operation
The device supports the I2 C protocol. This is summarized in Figure 8. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 8. I2 C bus protocol
Device operation M24C64-W M24C64-R M24C64-F
12/45 DocID16891 Rev 30
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
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4.5 Device addressing o start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
When the device select code is received, the device only responds if the Chip Enable
address is the same as the value on its Chip Enable E2,E1,E0 inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, the device deselects itself from the bus, and goes into Standby
mode.
Table 2. Device select code The most significant bit, b7, is sent first. E0, E1 and E2 are compared with the value read on input pins E0, E1,and E2.
Instructions M24C64-W M24C64-R M24C64-F
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5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address
bytes. The device responds to each address byte with an acknowledge bit, and then waits
for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 10.
Table 3. Most significant address byte
Table 4. Least significant address byte
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5.1.1 Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
Figure 9. Write mode sequences with WC = 0 (data write enabled)
Instructions M24C64-W M24C64-R M24C64-F
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5.1.2 Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 10. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 10. Write mode sequences with WC = 1 (data write inhibited)
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5.1.3 Write Identification Page (M24C64-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. It is written by issuing the Write Identification Page
instruction. This instruction uses the same protocol and format as Page Write (into memory
array), except for the following differences: Device type identifier = 1011b MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
5.1.4 Lock Identification Page (M24C64-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions: Device type identifier = 1011b Address bit A10 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care
5.1.5 ECC (Error Correction Code) and Write cycling
The ECC is offered only in devices identified with process letter K, all other devices
(identified with a different process letter) do not embed the ECC logic.
The Error Correction Code (ECC) is an internal logic function which is transparent for the 2 C communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(1) . Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(1) . As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the 4 bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined Table 11: Cycling performance. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.
Instructions M24C64-W M24C64-R M24C64-F
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5.1.6 Minimizing Write delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time
is shorter. To make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 11, is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1). The seven most significant bits of the Device Select code of a Random Read (bottom right box in the figure) must be identical to the seven most significant bits of the Device Select code of the Write (polling instruction in the figure).
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5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 12. Read mode sequences
Instructions M24C64-W M24C64-R M24C64-F
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5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 12) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 12, without acknowledging the byte.
Note that the address counter value is defined by instructions accessing either the memory
or the Identification page. When accessing the Identification page, the address counter
value is loaded with the byte location in the Identification page, therefore the next Current
Address Read in the memory uses this new address counter value. When accessing the
memory, it is safer to always use the Random Address Read instruction (this instruction
loads the address counter with the byte location to read in the memory, see Section 5.2.1)
instead of the Current Address Read instruction.
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 12.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
5.3 Read Identification Page (M24C64-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 10d, the number of bytes should be less than
or equal to 22, as the ID page boundary is 32 bytes).
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5.4 Read the lock status (M24C64-D only)
The locked/unlocked status of the Identification page can be checked by transmitting a
specific truncated command [Identification Page Write instruction + one data byte] to the
device. The device returns an acknowledge bit if the Identification page is unlocked,
otherwise a NoAck bit if the Identification page is locked.
Right after this, it is recommended to transmit to the device a Start condition followed by a
Stop condition, so that: Start: the truncated command is not executed because the Start condition resets the
device internal logic, Stop: the device is then set back into Standby mode by the Stop condition. Initial delivery state
The device is delivered with all the memory array bits and Identification page bits set to 1
(each byte contains FFh).
Maximum rating M24C64-W M24C64-R M24C64-F
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7 Maximum rating
Stressing the device outside the ratings listed in Table 5 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 5. Absolute maximum ratings Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). TLEAD max must not be applied for more than 10 s. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω). 4000 V for devices identified with process letter K and P.
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This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.
Table 6. Operating conditions (voltage range W) fCmax is 400 kHz devices identified by process letter P.
Table 7. Operating conditions (voltage range R) fCmax is 400 kHz devices identified by process letter P.
Table 8. Operating conditions (voltage range F) Only for devices identified with process letter T
