M24C16-RMC6TG ,16 Kbit serial I2C bus EEPROFeatures2• Compatible with all I C bus modes:– 400 kHz– 100 kHzTSSOP8 (DW)• Memory array:169 mil wi ..
M24C16-RMN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROMAbsolute Maximum Ratings . . . . . . . 132/29M24C16, M24C08, M24C04, M24C02, M24C01DC and AC PA ..
M24C16-RMN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROMLogic Diagrama Stop condition after an Ack for Write, and after aNoAck for Read.VCCTable 1. Signal ..
M24C16-RMN6T ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROMFEATURES SUMMARY2■ Two Wire I C Serial Interface Figure 1. PackagesSupports 400kHz Protocol■ Single ..
M24C16-RMN6TP ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROMLogic Diagrama Stop condition after an Ack for Write, and after aNoAck for Read.VCCTable 1. Signal ..
M24C16-W ,16KBIT, 8KBIT, 4KBIT, 2KBIT AND 1KBIT SERIAL I²C BUS EEPROMapplications where this signal is to be looked for on the three least significant bitsis used by sl ..
M38049FFFP , 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
M38049FFFP , 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
M38063E6FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38063E6FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38063E6FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38067M8-139FP , SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M24C16-RMC6TG
16 Kbit serial I2C bus EEPROM
September 2014 DocID023494 Rev 5 1/41
M24C16-W M24C16-R
M24C16-F16-Kbit serial I²C bus EEPROM
Datasheet - production data Features Compatible with all I2 C bus modes: 400 kHz 100 kHz Memory array: 16 Kbit (2 Kbytes) of EEPROM Page size: 16 bytes Single supply voltage: M24C16-W: 2.5 V to 5.5 V M24C16-R: 1.8 V to 5.5 V M24C16-F: 1.7 V to 5.5 V (full temperature
range) and 1.6 V to1.7 V (limited
temperature range) Write: Byte Write within 5 ms Page Write within 5 ms Operating temperature range: from -40 °C up to +85 °C Random and sequential Read modes Write protect of the whole memory array Enhanced ESD/Latch-Up protection More than 4 million Write cycles More than 200-year data retention
Packages PDIP8 ECOPACK1® SO8 ECOPACK2® TSSOP8 ECOPACK2® UFDFPN8 ECOPACK2® WLCSP ECOPACK2® UFDFPN5 ECOPACK2®
Contents M24C16-W M24C16-R M24C16-F2/41 DocID023494 Rev 5
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 Supply voltage (VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.1 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1.3 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 17
5.2 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
DocID023494 Rev 5 3/41
M24C16-W M24C16-R M24C16-F Contents Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
List of tables M24C16-W M24C16-R M24C16-F
4/41 DocID023494 Rev 5
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Address byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 5. Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 6. Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Operating conditions (voltage range F, for devices identified
by process letter T). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 8. Operating conditions (voltage range F, for all other devices) . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Cycling performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 12. Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 13. DC characteristics (M24C16-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC characteristics (M24C16-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. DC characteristics (M24C16-F device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. 100 kHz AC characteristics (I2 C Standard mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. UFDFPN5 (MLP5) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. UFDFPN8 (MLP8) – package dimensions (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
Table 21. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . . 33
Table 22. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 34
Table 23. M24C16-FCS5TP/S WLCSP 5 bumps package data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 25. Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DocID023494 Rev 5 5/41
M24C16-W M24C16-R M24C16-F List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. UFDFPN5 package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. M24C16-FCS5TP/S WLCSP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. I2 C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for
an I2C bus at maximum frequency fC = 400 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 13. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 14. UFDFPN5 (MLP5) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 15. UFDFPN8 (MLP8) – package outline (UFDFPN: Ultra thin Fine pitch
Dual Flat Package, No lead). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. SO8N – 8-lead plastic small outline, 150 mils body width, package outline. . . . . . . . . . . . 33
Figure 18. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 34
Figure 19. M24C16-FCS5TP/S WLCSP 5 bumps package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Description M24C16-W M24C16-R M24C16-F
6/41 DocID023494 Rev 5
1 Description
The M24C16 is a 16-Kbit I2 C-compatible EEPROM (Electrically Erasable PROgrammable
Memory) organized as 2 K × 8 bits.
The M24C16-W can be accessed (Read and Write) with a supply voltage from 2.5 V to
5.5 V, the M24C16-R can be accessed (Read and Write) with a supply voltage from 1.8 V to
5.5 V, and the M24C16-F can be accessed either with a supply voltage from 1.7 V to 5.5 V
(over the full temperature range) or with an extended supply voltage from 1.6 V to 1.7 V. All
these devices operate with a clock frequency of 400 kHz.
Figure 1. Logic diagram
Table 1. Signal names
DocID023494 Rev 5 7/41
M24C16-W M24C16-R M24C16-F Description
Figure 3. UFDFPN5 package connections See Section 9: Package mechanical data for package dimensions, and how to identify pin 1
Figure 4. M24C16-FCS5TP/S WLCSP connections
Signal description M24C16-W M24C16-R M24C16-F
8/41 DocID023494 Rev 5
2 Signal description
2.1 Serial Clock (SCL)
The signal applied on the SCL input is used to strobe the data available on SDA(in) and to
output the data on SDA(out).
2.2 Serial Data (SDA)
SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an
open drain output that may be wire-OR’ed with other open drain or open collector signals on
the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12
indicates how to calculate the value of the pull-up resistor).
2.3 Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either
driven low or left floating.
When Write Control (WC) is driven high, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
2.4 V SS (ground)
VSS is the reference for the VCC supply voltage.
2.5 Supply voltage (V CC)
2.5.1 Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a write instruction, until the completion of the internal write cycle (tW).
2.5.2 Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
(see Operating conditions in Section 8: DC and AC parameters) and the rise time must not
vary faster than 1 V/µs.
DocID023494 Rev 5 9/41
M24C16-W M24C16-R M24C16-F Signal description
2.5.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included.
At power-up, the device does not respond to any instruction until VCC has reached the
internal reset threshold voltage. This threshold is lower than the minimum VCC operating
voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes
over the POR threshold, the device is reset and enters the Standby Power mode; however,
the device must not be accessed until VCC reaches a valid and stable DC voltage within the
specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC
parameters).
In a similar way, during power-down (continuous decrease in VCC), the device must not be
accessed when VCC drops below VCC(min). When VCC drops below the threshold voltage,
the device stops responding to any instruction sent to it.
2.5.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in the Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
write cycle in progress).
Memory organization M24C16-W M24C16-R M24C16-F
10/41 DocID023494 Rev 5
3 Memory organization
The memory is organized as shown below.
Figure 5. Block diagram
DocID023494 Rev 5 11/41
M24C16-W M24C16-R M24C16-F Device operation
4 Device operation
The device supports the I2 C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
Figure 6. I2 C bus protocol
Device operation M24C16-W M24C16-R M24C16-F
12/41 DocID023494 Rev 5
4.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and
driven high. A Stop condition terminates communication between the device and the bus
master. A Read instruction that is followed by NoAck can be followed by a Stop condition to
force the device into the Standby mode.
A Stop condition at the end of a Write instruction triggers the internal Write cycle.
4.3 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
4.4 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
DocID023494 Rev 5 13/41
M24C16-W M24C16-R M24C16-F Device operation
4.5 Device addressing o start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 2. Device select code The most significant bit, b7, is sent first.
Instructions M24C16-W M24C16-R M24C16-F
14/41 DocID023494 Rev 5
5 Instructions
5.1 Write operations
Following a Start condition the bus master sends a device select code with the R/W bit (RW)
reset to 0. The device acknowledges this, as shown in Figure 7, and waits for the address
byte. The device responds to each address byte with an acknowledge bit, and then waits for
the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal
Write cycle.
After the Stop condition and the successful completion of an internal Write cycle (tW), the
device internal address counter is automatically incremented to point to the next byte after
the last modified byte.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
Table 3. Address byte
DocID023494 Rev 5 15/41
M24C16-W M24C16-R M24C16-F Instructions
5.1.1 Byte Write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 7.
Figure 7. Write mode sequences with WC = 0 (data write enabled)
Instructions M24C16-W M24C16-R M24C16-F
16/41 DocID023494 Rev 5
5.1.2 Page Write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A10/A4, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 8. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 8. Write mode sequences with WC = 1 (data write inhibited)
DocID023494 Rev 5 17/41
M24C16-W M24C16-R M24C16-F Instructions
5.1.3 Minimizing Write delays by polling on ACK
The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC
parameters, but the typical time is shorter. To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 9, is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Instructions M24C16-W M24C16-R M24C16-F
18/41 DocID023494 Rev 5
5.2 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Figure 10. Read mode sequences
DocID023494 Rev 5 19/41
M24C16-W M24C16-R M24C16-F Instructions
5.2.1 Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 10) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the RW bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a Stop condition.
5.2.2 Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 10, without acknowledging the byte.
5.2.3 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 10.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter “rolls-over”, and the device continues to output data from memory address
00h.
Initial delivery state M24C16-W M24C16-R M24C16-F
20/41 DocID023494 Rev 5 Initial delivery state
The device is delivered with all the memory array bits set to 1 (each byte contains FFh).
DocID023494 Rev 5 21/41
M24C16-W M24C16-R M24C16-F Maximum rating
7 Maximum rating
Stressing the device outside the ratings listed in Table 4 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 4. Absolute maximum ratings Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). TLEAD max must not be applied for more than 10 s. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω). 4000 V for devices identified by process letters S or G.
