M24C08-MN6T ,16/8/4/2/1 Kbit Serial IC Bus EEPROMM24C16, M24C08M24C04, M24C02, M24C0116/8/4/2/1 Kbit Serial I²C Bus EEPROM2■ Two Wire I C Serial Int ..
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M24C01MN1T-M24C01MN3T-M24C01MN6T-M24C01-MN6T-M24C01WMN6T-M24C02-MN6T-M24C04MN3T-M24C04MN6T-M24C04-MN6T-M24C08-BN6T-M24C08MN6T-M24C08-MN6T-M24C08WDW6T-M24C16-BN6T-M24C16MN1T-M24C16MN3T-M24C16MN6T-M24C16-MN6T -M24C16RDW6T-M24C16WMN6T
16/8/4/2/1 Kbit Serial IC Bus EEPROM
1/20May 2000
M24C16, M24C08
M24C04, M24C02, M24C0116/8/4/2/1 Kbit Serial I²C Bus EEPROM Two Wire I2 C Serial Interface
Supports 400 kHz Protocol Single Supply Voltage: 4.5V to 5.5V for M24Cxx 2.5V to 5.5V for M24Cxx-W 1.8V to 3.6V for M24Cxx-R Hardware Write Control BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior 1 Million Erase/Write Cycles (minimum) 40 Year Data Retention (minimum)
DESCRIPTIONThese I2 C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 bit
(M24C16, M24C08, M24C04, M24C02, M24C01),
and operate with a power supply down to 2.5 V (for
the -W version of each device), and down to 1.8V
(for the -R version of each device).
The M24C16, M24C08, M24C04, M24C02,
M24C01 are available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small
Outline packages. The M24C16-R is also
available in a chip-scale (SBGA) package.
Table 1. Signal Names
M24C16, M24C08, M24C04, M24C02, M24C01
3/20
M24C16, M24C08, M24C04, M24C02, M24C01These memory devices are compatible with the2 C memory standard. This is a two wire serial
interface that uses a bi-directional data bus and
serial clock. The memory carries a built-in 4-bit
unique Device Type Identifier code (1010) in
accordance with the I2 C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Power On Reset: VCC Lock-Out Write ProtectIn order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until the VCC voltage has reached
the POR threshold value, and all operations are
Table 2. Absolute Maximum Ratings 1Note:1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. MIL-STD-883C, 3015.7 (100 pF, 1500 Ω)
M24C16, M24C08, M24C04, M24C02, M24C01disabled – the device will not respond to any
command. In the same way, when VCC drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable and
valid VCC must be applied before applying any
logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a
slower clock, the master must have an open drain
output, and a pull-up resistor must be connected
from the SCL line to VCC. (Figure 3 indicates how
the value of the pull-up resistor can be calculated).
In most applications, though, this method of
synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the
master has a push-pull (rather than open drain)
output.
Serial Data (SDA)The SDA pin is bi-directional, and is used to
transfer data in or out of the memory. It is an open
drain output that may be wire-OR’ed with other
open drain or open collector signals on the bus. A
pull up resistor must be connected from the SDA
bus to VCC. (Figure 3 indicates how the value of
the pull-up resistor can be calculated).
Chip Enable (E2, E1, E0)These chip enable inputs are used to set the value
that is to be looked for on the three least significant
bits (b3, b2, b1) of the 7-bit device select code (but
see the description of memory addressing, on
page 6, for more details). These inputs may be
driven dynamically or tied to VCC or VSS to
establish the device select code (but note that the
VIL and VIH levels for the inputs are CMOS
compatible, not TTL compatible).
5/20
M24C16, M24C08, M24C04, M24C02, M24C01
Write Control (WC)The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not
acknowledged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION The memory device supports the I2 C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all
communication.
Start ConditionSTART is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device
continuously monitors (except during a
programming cycle) the SDA and SCL lines for a
START condition, and will not respond unless one
is given.
Stop ConditionSTOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates
communication between the memory device and
the bus master. A STOP condition at the end of a
Read command, after (and only after) a NoAck,
forces the memory device into its standby state. A
STOP condition at the end of a Write command
triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK)An acknowledge signal is used to indicate a
successful byte transfer. The bus transmitter,
whether it be master or slave, releases the SDA
bus after sending eight bits of data. During the 9th
Table 3. Device Select Code 1Note:1. The most significant bit, b7, is sent first. E0, E1 and E2 are compared against the respective external pins on the memory device. A10, A9 and A8 represent high significant bits of the address.
Table 4. Operating ModesNote:1. X = VIH or VIL.
M24C16, M24C08, M24C04, M24C02, M24C01clock pulse period, the receiver pulls the SDA bus
low to acknowledge the receipt of the eight data
bits.
Data InputDuring data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
must be stable during the clock low-to-high
transition, and the data must change only when
the SCL line is low.
Memory AddressingTo start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is
further subdivided into: a 4-bit Device Type
Identifier, and a 3-bit Chip Enable “Address” (E2,
E1, E0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2 C bus. Each one is given a unique 3-bit
code on its Chip Enable inputs. When the Device
Select Code is received, the memory only
responds if the Chip Enable Code (shown in Table
3) is the same as the pattern applied to its Chip
Enable pins.
Those devices with larger memory capacities (the
M24C16, M24C08 and M24C04) need more
address bits. E0 is not available for use on devices
that need to use address line A8; E1 is not
available for devices that need to use address line
A9, and E2 is not available for devices that need to
use address line A10 (see Figure 2A to Figure 2D
and Table 3 for details). Using the E0, E1 and E2
inputs pins, up to eight M24C02 (or M24C01), four
M24C04, two M24C08 or one M24C16 device can
be connected to one I2 C bus. In each case, and in
the hybrid cases, this gives a total memory
7/20
M24C16, M24C08, M24C04, M24C02, M24C01capacity of 16 Kbits, 2 KBytes (except where
M24C01 devices are used).
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding
memory gives an acknowledgment on the SDA
bus during the 9th bit time. If the memory does not
match the Device Select Code, it deselects itself
from the bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Write Operations Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for an address byte. The memory
responds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the address byte) will not
modify the memory contents, and the
accompanying data bytes will not be
acknowledged (as shown in Figure 5).
Byte WriteIn the Byte Write mode, after the Device Select
Code and the address, the master sends one data
byte. If the addressed location is write protected by
the WC pin, the memory replies with a NoAck, and
the location is not modified. If, instead, the WC pin
has been held at 0, as shown in Figure 6, the
memory replies with an Ack. The master
terminates the transfer by generating a STOP
condition.
Page WriteThe Page Write mode allows up to 16 bytes to be
written in a single write cycle, provided that they
M24C16, M24C08, M24C04, M24C02, M24C01A STOP condition at any other time does not
trigger the internal write cycle.
During the internal write cycle, the SDA input is
disabled internally, and the device does not
respond to any requests.
Minimizing System Delays by Polling On ACKDuring the internal write cycle, the memory
disconnects itself from the bus, and copies the
data from its internal latches to the memory cells.
The maximum write time (tw) is shown in Table 6B,
but the typical time is shorter. To make use of this,
an Ack polling sequence can be used by the
master.
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-
over’ occurs. Data starts to become overwritten, or
otherwise altered.
The master sends from one up to 16 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the
contents of the addressed memory location are
not modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 4 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
9/20
M24C16, M24C08, M24C04, M24C02, M24C01
Read OperationsRead operations are performed independently of
the state of the WC pin.
Random Address ReadA dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the
master sends another START condition, and
repeats the Device Select Code, with the RW bit
set to ‘1’. The memory acknowledges this, and
outputs the contents of the addressed byte. The
master must not acknowledge the byte output, and
terminates the transfer with a STOP condition.
The sequence, as shown in Figure 7, is: Initial condition: a Write is in progress. Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction). Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the
master goes back to Step 1. If the memory has
terminated the internal write cycle, it responds
with an Ack, indicating that the memory is ready
to receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
M24C16, M24C08, M24C04, M24C02, M24C01
Table 5A. DC Characteristics(TA = 0 to 70 °C, or –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5V)
(TA = 0 to 70 °C, or –40 to 85 °C; VCC = 1.8 to 3.6 V)
Note:1. This is preliminary data.
Current Address ReadThe device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory
acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The master
terminates the transfer with a STOP condition, as
shown in Figure 8, without acknowledging the byte
output.
Sequential ReadThis mode can be initiated with either a Current
Address Read or a Random Address Read. The
master does acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must not acknowledge the last
byte output, and must generate a STOP condition.
The output data comes from consecutive
addresses, with the internal address counter
automatically incremented after each byte output.
After the last memory address, the address
counter ‘rolls-over’ and the memory continues to
output data from memory address 00h.
Acknowledge in Read ModeIn all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
