M24C02W ,16/8/4/2/1 KBIT SERIAL I2C BUS EEPROMM24C16, M24C08M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
M24C02-W ,16/8/4/2/1 KBIT SERIAL I2C BUS EEPROMLogic DiagramWhen data is read by the bus master, the busmaster acknowledges the receipt of the dat ..
M24C02-WBN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROMLogic Diagrama Stop condition after an Ack for Write, and after aNoAck for Read.VCCTable 1. Signal ..
M24C02-WBN6 ,16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial IC Bus EEPROMFEATURES SUMMARY2■ Two Wire I C Serial Interface Figure 1. PackagesSupports 400kHz Protocol■ Single ..
M24C02WBN6P ,2 Kbit serial I2C bus EEPROMLogic diagram . . . . 6Figure 2. 8-pin package connections, top view . . 6Figure 3.
M24C02-WBN6P ,2 Kbit serial I2C bus EEPROMFeatures2• Compatible with all I C bus modes:– 400 kHz– 100 kHzTSSOP8 (DW)• Memory array:169 mil wi ..
M38002E2FP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M38002E2SP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M38002E2SP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M38002E2SP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M38002E4FP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M38002M4-259SP , 8-BIT SINGLE-CHIP MICROCOMPUTER
M24C01-M24C02-M24C02-R-M24C02W-M24C02-W-M24C04-M24C08-M24C16-M24C16-W
16KBIT, 8KBIT, 4KBIT, 2KBIT AND 1KBIT SERIAL I²C BUS EEPROM
1/26February 2003
M24C16, M24C08
M24C04, M24C02, M24C0116Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I²C Bus EEPROM
FEATURES SUMMARY Two Wire I2 C Serial Interface
Supports 400 kHz Protocol Single Supply Voltage: 4.5V to 5.5V for M24Cxx 2.5V to 5.5V for M24Cxx-W 2.2V to 5.5V for M24Cxx-L 1.8V to 5.5V for M24Cxx-R 1.8V to 3.6V for M24Cxx-S Write Control Input BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
Figure 1. Packages
M24C16, M24C08, M24C04, M24C02, M24C01
SUMMARY DESCRIPTIONThese I2 C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128x8
(M24C16, M24C08, M24C04, M24C02, M24C01).
Figure 2. Logic DiagramThese devices are compatible with the I2 C memo-
ry protocol. This is a two wire serial interface that
uses a bi-directional data bus and serial clock. The
devices carry a built-in 4-bit Device Type Identifier
code (1010) in accordance with the I2 C bus defini-
tion.
The device behaves as a slave in the I2 C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat-
ed by a Start condition, generated by the bus mas-
ter. The Start condition is followed by a Device
Select Code and RW bit (as described in Table 2),
terminated by an acknowledge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Table 1. Signal Names
Power On Reset: VCC Lock-Out Write ProtectIn order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command. A stable and valid VCC must be
applied before applying any logic signal.
Figure 3. DIP, SO and TSSOP ConnectionsNote:1. NC = Not Connected See page 20 (onwards) for package dimensions, and how to identify pin-1.
3/26
M24C16, M24C08, M24C04, M24C02, M24C01
SIGNAL DESCRIPTION
Serial Clock (SCL)This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to VCC. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. These
inputs must be tied to VCC or VSS, to establish the
Device Select Code.
Write Control (WC)This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
ternally read as VIL, and Write operations are al-
lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 5. I2 C Bus Protocol
Table 2. Device Select CodeNote:1. The most significant bit, b7, is sent first. E0, E1 and E2 are compared against the respective external pins on the memory device. A10, A9 and A8 represent most significant bits of the address.
5/26
M24C16, M24C08, M24C04, M24C02, M24C01
DEVICE OPERATION The device supports the I2 C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device. data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24Cxx device is always a
slave in all communication.
Start ConditionStart is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop ConditionStop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During theth clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data InputDuring data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory AddressingTo start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
When the Device Select Code is received on Seri-
al Data (SDA), the device only responds if the Chip
Enable Address is the same as the value on the
Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Devices with larger memory capacities (the
M24C16, M24C08 and M24C04) need more ad-
dress bits. E0 is not available for use on devices
that need to use address line A8; E1 is not avail-
able for devices that need to use address line A9,
and E2 is not available for devices that need to use
address line A10 (see Figure 3 and Table 2 for de-
tails). Using the E0, E1 and E2 inputs pins, up to
eight M24C02 (or M24C01), four M24C04, two
M24C08 or one M24C16 device can be connected
to one I2 C bus. In each case, and in the hybrid cas-
es, this gives a total memory capacity of 16 Kbits, KBytes (except where M24C01 devices are
used).
Table 3. Operating ModesNote:1. X = VIH or VIL.
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
7, and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte WriteAfter the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in Figure 6, and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in Figure 7.
Page WriteThe Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
7/26
M24C16, M24C08, M24C04, M24C02, M24C01condition until the end of the address byte), the de-
vice replies to the data bytes with NoAck, as
shown in Figure 6, and the locations are not mod-
ified. After each byte is transferred, the internal
byte address counter (the 4 least significant ad-
dress bits only) is incremented. The transfer is ter-
minated by the bus master generating a Stop
condition.
Figure 7. Write Mode Sequences with WC=0 (data write enabled)
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 8. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACKDuring the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Tables
19 to 21, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 8, is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction). Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
9/26
M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode SequencesNote:1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read OperationsRead operations are performed independently of
the state of the Write Control (WC) signal.
Random Address ReadA dummy Write is performed to load the address
into the address counter (as shown in Figure 9) but
without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats
the Device Select Code, with the RW bit set to 1.
The device acknowledges this, and outputs the
contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address ReadThe device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
transfer with a Stop condition, as shown in Figure
9, without acknowledging the byte.
Sequential ReadThis operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
M24C16, M24C08, M24C04, M24C02, M24C01master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read ModeFor all Read commands, the device waits, after
each byte read, for an acknowledgment during theth bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
11/26
M24C16, M24C08, M24C04, M24C02, M24C01
MAXIMUM RATINGStressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum RatingsNote:1. IPC/JEDEC J-STD-020A JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
M24C16, M24C08, M24C04, M24C02, M24C01
DC AND AC PARAMETERSThis section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 5. Operating Conditions (M24Cxx-xx6)
Table 6. Operating Conditions (M24Cxx-xx3)
Table 7. Operating Conditions (M24Cxx-Wxx6)
Table 8. Operating Conditions (M24Cxx-Lxx6)
Table 9. Operating Conditions (M24Cxx-Rxx6)
Table 10. Operating Conditions (M24Cxx-Sxx6)
13/26
M24C16, M24C08, M24C04, M24C02, M24C01
Table 11. AC Measurement Conditions
Figure 10. AC Measurement I/O Waveform
Table 12. Input ParametersNote:1. TA = 25 °C, f = 400 kHz Sampled only, not 100% tested.
