M24164-WMN1-M24164-WMN1T Fast Delivery |IC PHOENIX CO.,LIMITED

M24164-WMN1 ,16 KBIT SERIAL I²C BUS EEPROM WITH 1 INVERTING AND 2 NON-INVERTING CHIP ENABLE LINESLogic DiagramNoAck for Read.Figure 3. DIP ConnectionsVCC3M24164E0-E2 SDAE0 1 8 VCCM24164SCLE1 2 7 W ..
M24164-WMN1T ,16 KBIT SERIAL I²C BUS EEPROM WITH 1 INVERTING AND 2 NON-INVERTING CHIP ENABLE LINESFEATURES SUMMARY2■ Two Wire I C Serial Interface Figure 1. PackagesSupports 400 kHz Protocol■ Singl ..
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M24164-WMN1-M24164-WMN1T
16 KBIT SERIAL I²C BUS EEPROM WITH 1 INVERTING AND 2 NON-INVERTING CHIP ENABLE LINES
1/21October 2001
M24164
16 Kbit Serial I²C Bus EEPROM
with 1 Inverting and 2 Non-Inverting Chip Enable Lines
FEATURES SUMMARY Two Wire I2 C Serial Interface
Supports 400 kHz Protocol Single Supply Voltage: 4.5V to 5.5V for M24164 2.5V to 5.5V for M24164-W Write Control Input BYTE and PAGE WRITE (up to 16 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 1 Million Erase/Write Cycles More than 40 Year Data Retention
Figure 1. Packages
M24164
SUMMARY DESCRIPTION
The M24164 is a 16 Kbit (2048 x 8) electrically
erasable programmable memory (EEPROM) ac-
cessed by an I2 C-compatible bus.
Figure 2. Logic Diagram
Table 1. Signal Names
These devices are compatible with a two-wire se-
rial interface that uses a bi-directional data bus
and serial clock. By setting the three chip enables
(E0, E1, E2) appropriately, up to eight 16 Kbit de-
vices can be attached to the same I2 C bus, and
selected individually.
These devices behave as slave devices, with all
memory operations synchronized by the serial
clock. Read and Write operations are initiated by a
Start condition, generated by the bus master. The
Start condition is followed by a Device Select
Code and RW bit (as described in Table 2), termi-
nated by an acknowledge bit.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
Figure 3. DIP Connections
Figure 4. SO Connections
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during Power-up, a Power On
Reset (POR) circuit is included. The internal reset
is held active until VCC has reached the POR
threshold value, and all operations are disabled –
the device will not respond to any command. In the
same way, when VCC drops from the operating
voltage, below the POR threshold value, all oper-
ations are disabled and the device will not respond
to any command. A stable and valid VCC must be
applied before applying any logic signal.
3/21
M24164
SIGNAL DESCRIPTION
Serial Clock (SCL)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor must be con-
nected from Serial Clock (SCL) to VCC. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
Serial Data (SDA)
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Chip Enable (E0, E1, E2)
These input signals are used to set the value that
is to be looked for on three bits (b6, b5, b4) of the
7-bit Device Select Code. These inputs must be
tied to VCC or VSS, to establish the Device Select
Code.
Write Control (WC)
This input signal is useful for protecting the entire
contents of the memory from inadvertent write op-
erations. Write operations are disabled to the en-
tire memory array when Write Control (WC) is
driven High. When unconnected, the signal is in-
ternally read as VIL, and Write operations are al-
lowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
M24164
DEVICE OPERATION
The device supports the I2 C protocol. This is sum-
marized in Figure 2. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device. data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The M24164 device is always a
slave in all communication.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During theth clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends eight bits, on Serial Data (SDA), most signif-
icant bit first. These consist of the 7-bit Device Se-
lect Code, and the Read/Write bit (RW), as shown
in Table 2. This last bit is set to 1 for Read, and 0
for Write operations.
The Device Select Code contains the three most
significant bits of the address within the memory
(A10, A9, A8), and a 3-bit Chip Enable “Address”
(E2, E1, E0).
When the Device Select Code is received on Seri-
al Data (SDA), the device only responds if the Chip
Enable Address is the same as the value on the
Chip Enable (E0, E2, and the inverse of E1) in-
puts. Up to eight devices can be connected on the
same bus, giving a total memory capacity of
128 Kbits, 16 KBytes.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 2. Device Select Code 1
Note:1. The most significant bit, b7, is sent first.
5/21
M24164
Figure 6. I2 C Bus Protocol
Table 3. Operating Modes
Note:1. X = VIH or VIL.
M24164
Figure 7. Write Mode Sequences with WC=1 (data write inhibited)
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the address byte) will not modify the memory con-
tents, and the accompanying data bytes are not
acknowledged, as shown in Figure 7.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High, the device replies with
NoAck, and the location is not modified. If, instead,
the addressed location is not Write-protected, the
device replies with Ack. The bus master termi-
nates the transfer by generating a Stop condition,
as shown in Figure 8.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
7/21
M24164
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 4 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
M24164
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Tables
11 and 12, but the typical time is shorter. To make
use of this, a polling sequence can be used by the
bus master.
The sequence, as shown in Figure 9, is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction). Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
9/21
M24164
Figure 10. Read Mode Sequences
Note:1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
Random Address Read
A dummy Write is performed to load the address
into the address counter (as shown in Figure 10)
but without sending a Stop condition. Then, the
bus master sends another Start condition, and re-
peats the Device Select Code, with the RW bit set
to 1. The device acknowledges this, and outputs
the contents of the addressed byte. The bus mas-
ter must not acknowledge the byte, and terminates
the transfer with a Stop condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read operation, following a Start
condition, the bus master only sends a Device Se-
lect Code with the RW bit set to 1. The device ac-
knowledges this, and outputs the byte addressed
by the internal address counter. The counter is
then incremented. The bus master terminates the
M24164
transfer with a Stop condition, as shown in Figure
10, without acknowledging the byte.
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 10.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during theth bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
11/21
M24164
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 4. Absolute Maximum Ratings
Note:1. IPC/JEDEC J-STD-020A JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

Partno	Mfg	Dc	Qty	Available	Descript
M24164-WMN1 \|M24164WMN1	ST	N/a	78280	avai	16 KBIT SERIAL I²C BUS EEPROM WITH 1 INVERTING AND 2 NON-INVERTING CHIP ENABLE LINES
M24164-WMN1T \|M24164WMN1T	ST	N/a	39881	avai	16 KBIT SERIAL I²C BUS EEPROM WITH 1 INVERTING AND 2 NON-INVERTING CHIP ENABLE LINES