M24128 Fast Delivery |IC PHOENIX CO.,LIMITED

M24128 ,256/128 KBIT SERIAL I2C BUS EEPROM WITHOUT CHIP ENABLE LINESLogic DiagramThe M24256B, M24128B and M24256A are alsoavailable, and offer the extra functionality ..
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M24128
256/128 KBIT SERIAL I2C BUS EEPROM WITHOUT CHIP ENABLE LINES
1/17June 2001
M24256
M24128
256/128 Kbit Serial I²C Bus EEPROM
Without Chip Enable Lines Compatible with I2 C Extended Addressing Two Wire I2 C Serial Interface
Supports 400 kHz Protocol Single Supply Voltage: 4.5V to 5.5V for M24xxx 2.5V to 5.5V for M24xxx-W Hardware Write Control BYTE and PAGE WRITE (up to 64 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than 100,000 Erase/Write Cycles More than 40 Year Data Retention
DESCRIPTION
These I2 C-compatible electrically erasable pro-
grammable memory (EEPROM) devices are orga-
nized as 32Kx8 bits (M24256) and 16Kx8 bits
(M24128), and operate down to 2.5 V (for the -W
version of each device).
The M24256B, M24128B and M24256A are also
available, and offer the extra functionality of the
chip enable inputs. Please see the separate data
sheets for details of these products.
The M24256 and M24128 are available in Plastic
Dual-in-Line and Plastic Small Outline packages.
These memory devices are compatible with the2 C extended memory standard. This is a two wire
Figure 1. Logic Diagram
Table 1. Signal Names
M24256, M24128
serial interface that uses a bi-directional data bus
and serial clock. The memory carries a built-in 4-
bit unique Device Type Identifier code (1010) in
accordance with the I2 C bus definition.
The memory behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Device Select Code and RW bit (as described in
Table 3), terminated by an acknowledge bit.
When writing data to the memory, the memory in-
serts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and af-
ter a NoAck for READ.
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
write operations during power up, a Power On Re-
set (POR) circuit is included. The internal reset is
held active until the VCC voltage has reached the
POR threshold value, and all operations are dis-
abled – the device will not respond to any com-
mand. In the same way, when VCC drops from the
operating voltage, below the POR threshold value,
all operations are disabled and the device will not
respond to any command. A stable and valid VCC
must be applied before applying any logic signal.
SIGNAL DESCRIPTION
Serial Clock (SCL)
The SCL input pin is used to strobe all data in and
out of the memory. In applications where this line
is used by slaves to synchronize the bus to a slow-
Figure 2A. DIP Connections
Note:1. NC = Not Connected
Figure 2B. SO Connections
Note:1. NC = Not Connected
Table 2. Absolute Maximum Ratings 1
Note:1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. IPC/JEDEC J-STD-020A JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
3/17
M24256, M24128
er clock, the master must have an open drain out-
put, and a pull-up resistor must be connected from
the SCL line to VCC. (Figure 3 indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the master has
a push-pull (rather than open drain) output.
Serial Data (SDA)
The SDA pin is bi-directional, and is used to trans-
fer data in or out of the memory. It is an open drain
output that may be wire-OR’ed with other open
drain or open collector signals on the bus. A pull
up resistor must be connected from the SDA bus
to VCC. (Figure 3 indicates how the value of the
pull-up resistor can be calculated).
Write Control (WC)
The hardware Write Control pin (WC) is useful for
protecting the entire contents of the memory from
inadvertent erase/write. The Write Control signal is
used to enable (WC=VIL) or disable (WC=VIH)
write instructions to the entire memory area. When
unconnected, the WC input is internally read as
VIL, and write operations are allowed.
When WC=1, Device Select and Address bytes
are acknowledged, Data bytes are not acknowl-
edged.
Please see the Application Note AN404 for a more
detailed description of the Write Control feature.
DEVICE OPERATION
The memory device supports the I2 C protocol.
This is summarized in Figure 4, and is compared
with other serial bus protocols in Application Note
AN1001. Any device that sends data on to the bus
is defined to be a transmitter, and any device that
reads the data to be a receiver. The device that
controls the data transfer is known as the master,
and the other as the slave. A data transfer can only
be initiated by the master, which will also provide
the serial clock for synchronization. The memory
device is always a slave device in all communica-
tion.
Start Condition
START is identified by a high to low transition of
the SDA line while the clock, SCL, is stable in the
high state. A START condition must precede any
data transfer command. The memory device con-
tinuously monitors (except during a programming
cycle) the SDA and SCL lines for a START condi-
tion, and will not respond unless one is given.
Stop Condition
STOP is identified by a low to high transition of the
SDA line while the clock SCL is stable in the high
state. A STOP condition terminates communica-
tion between the memory device and the bus mas-
ter. A STOP condition at the end of a Read
command, after (and only after) a NoAck, forces
the memory device into its standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK)
An acknowledge signal is used to indicate a suc-
cessful byte transfer. The bus transmitter, whether
it be master or slave, releases the SDA bus after
sending eight bits of data. During the 9th clock
pulse period, the receiver pulls the SDA bus low to
acknowledge the receipt of the eight data bits.
Data Input
During data input, the memory device samples the
SDA bus signal on the rising edge of the clock,
SCL. For correct device operation, the SDA signal
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS) for an I2 C Bus
M24256, M24128
must be stable during the clock low-to-high transi-
tion, and the data must change only when the SCL
line is low.
Memory Addressing
To start communication between the bus master
and the slave memory, the master must initiate a
START condition. Following this, the master sends
the 8-bit byte, shown in Table 3, on the SDA bus
line (most significant bit first). This consists of the
7-bit Device Select Code, and the 1-bit Read/Write
Designator (RW). The Device Select Code is fur-
ther subdivided into: a 4-bit Device Type Identifier,
and a 3-bit Chip Enable “Address” (0, 0, 0).
To address the memory array, the 4-bit Device
Type Identifier is 1010b.
The 8th bit is the RW bit. This is set to ‘1’ for read
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9th bit time. If the memory does not match
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
Figure 4. I2 C Bus Protocol
Table 3. Device Select Code 1
Note:1. The most significant bit, b7, is sent first.
5/17
M24256, M24128
There are two modes both for read and write.
These are summarized in Table 4 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 5) is sent first, followed by the Least significant
Byte (Table 6). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256 memory. Bits b15 and b14
are treated as Don’t Care bits on the M24128
memory.
Table 4. Operating Modes
Note:1. X = VIH or VIL.
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
M24256, M24128
Figure 6. Write Mode Sequences with WC=0 (data write enabled)
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 4. The memory acknowledges this,
and waits for two address bytes. The memory re-
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256 and b13-b6 for the
M24128) are the same. If more bytes are sent than
Table 5. Most Significant Byte
Note:1. b15 is treated as Don’t Care on the M24256 series.
b15 and b14 are Don’t Care on the M24128 series.
Table 6. Least Significant Byte
7/17
M24256, M24128
During the internal write cycle, the SDA input is
disabled internally, and the device does not re-
spond to any requests.
Minimizing System Delays by Polling On ACK
During the internal write cycle, the memory discon-
nects itself from the bus, and copies the data from
its internal latches to the memory cells. The maxi-
mum write time (tw) is shown in Table 10, but the
typical time is shorter. To make use of this, an Ack
polling sequence can be used by the master.
The sequence, as shown in Figure 7, is: Initial condition: a Write is in progress. Step 1: the master issues a START condition
followed by a Device Select Code (the first byte
of the new instruction). Step 2: if the memory is busy with the internal
write cycle, no Ack will be returned and the mas-
ter goes back to Step 1. If the memory has ter-
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. Data starts to become over-
written (in a way not formally specified in this data
sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10th bit” time
slot), either at the end of a byte write or a page
write, the internal memory write cycle is triggered.
A STOP condition at any other time does not trig-
ger the internal write cycle.
Figure 7. Write Cycle Polling Flowchart using ACK
M24256, M24128
the Device Select Code, with the RW bit set to ‘1’.
The memory acknowledges this, and outputs the
contents of the addressed byte. The master must
not acknowledge the byte output, and terminates
the transfer with a STOP condition.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read. For the
Current Address Read mode, following a START
condition, the master sends a Device Select Code
with the RW bit set to ‘1’. The memory acknowl-
edges this, and outputs the byte addressed by the
internal address counter. The counter is then in-
minated the internal write cycle, it responds with
an Ack, indicating that the memory is ready to
receive the second part of the next instruction
(the first byte of this instruction having been sent
during Step 1).
Read Operations
Read operations are performed independently of
the state of the WC pin.
Random Address Read
A dummy write is performed to load the address
into the address counter, as shown in Figure 8.
Then, without sending a STOP condition, the mas-
ter sends another START condition, and repeats
Figure 8. Read Mode Sequences
Note:1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.
9/17
M24256, M24128
Table 7. DC Characteristics
(TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.5 to 5.5V)
Table 8. Input Parameters1 (TA = 25 °C, f = 400 kHz)
Note:1. Sampled only, not 100% tested.
Table 9. AC Measurement Conditions
Figure 9. AC Testing Input Output Waveforms

Partno	Mfg	Dc	Qty	Available	Descript
M24128	ST	N/a	260	avai	256/128 KBIT SERIAL I2C BUS EEPROM WITHOUT CHIP ENABLE LINES