M24256-BWDW6TP ,256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable LinesFEATURES SUMMARY2■ Compatible with I C Extended Addressing Figure 1. Packages2■ Two-Wire I C Serial ..
M24256-BWDW6TP ,256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable LinesM24128-BW, M24128-BRM24256-BW, M24256-BR256Kbit and 128Kbit Serial I²C Bus EEPROMWith Three Chip En ..
M24256BWMN6 ,256Kbit and 128Kbit Serial IC Bus EEPROM With Three Chip Enable LinesLogic Diagram . . 4Table 1. Signal Names . . 4Power On Reset: VCC Lock-Out Write Prot ..
M24256-BWMN6 ,256Kbit and 128Kbit Serial IC Bus EEPROM With Three Chip Enable LinesFEATURES SUMMARY2■ Compatible with I C Extended Addressing Figure 1. Packages2■ Two Wire I C Serial ..
M24256-BWMN6P ,256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable LinesAbsolute Maximum Ratings . . . . . . . 132/25M24128-BW, M24128-BR, M24256-BW, M24256-BRDC AND A ..
M24256-BWMN6T ,256Kbit and 128Kbit Serial IC Bus EEPROM With Three Chip Enable LinesLogic DiagramNoAck for Read.Power On Reset: V Lock-Out Write ProtectCCIn order to prevent data corr ..
M37902FJCHP , SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37903S4CHP , 16-BIT CMOS MICROCOMPUTER
M37905F8CFP , 16-BIT CMOS MICROCOMPUTER
M37905F8CFP , 16-BIT CMOS MICROCOMPUTER
M37906F8CSP , 16-BIT CMOS MICROCOMPUTER
M37920FGCGP , SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M24128-BRDW6TP-M24128-BRMN6TP-M24128-BWDW6TP-M24256-BRMN6P-M24256-BRMN6TP-M24256-BRMW6TP-M24256-BWDW6TP-M24256-BWMN6P-M24256-BWMN6TP-M24256-BWMW6G-M24256-BWMW6TG
256Kbit and 128Kbit Serial I2C Bus EEPROM With Three Chip Enable Lines
1/25June 2005
M24128-BW, M24128-BR
M24256-BW, M24256-BR256Kbit and 128Kbit Serial I²C Bus EEPROM
With Three Chip Enable Lines
FEATURES SUMMARY Compatible with I2 C Extended Addressing Two-Wire I2 C Serial Interface
Supports 400kHz Protocol Single Supply Voltage: 2.5 to 5.5V for M24128-BW, M24256-BW 1.8 to 5.5V for M24128-BR, M24256-BR Hardware Write Control BYTE and PAGE WRITE (up to 64 Bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40-Year Data Retention
Table 1. Product List
M24128-BW, M24128-BR, M24256-BW, M24256-BR
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . .5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . .8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Table 8. Operating Conditions (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 9. Operating Conditions (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 11. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 12. DC Characteristics (M24128-BW, M24256-BW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 13. DC Characteristics (M24128-BR, M24256-BR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Table 14. AC Characteristics ( M24128-BW, M24256-BW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 15. AC Characteristics (M24128-BR, M24256-BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .19
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . .19
Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .20
Table 17. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
Figure 14.SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Outline. . . . . .21
Table 18. SO8 wide – 8 lead Plastic Small Outline, 200 mils body width, Package Mechanical Data
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .22
Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . .22
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
M24128-BW, M24128-BR, M24256-BW, M24256-BR
5/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to
strobe all data in and out of the device. In applica-
tions where this signal is used by slave devices to
synchronize the bus to a slower clock, the bus
master must have an open drain output, and a
pull-up resistor must be connected from Serial
Clock (SCL) to VCC. (Figure 4. indicates how the
value of the pull-up resistor can be calculated). In
most applications, though, this method of synchro-
nization is not employed, and so the pull-up resis-
tor is not necessary, provided that the bus master
has a push-pull (rather than open drain) output.
Serial Data (SDA). This bi-directional signal is
used to transfer data in or out of the device. It is an
open drain output that may be wire-OR’ed with
other open drain or open collector signals on the
bus. A pull up resistor must be connected from Se-
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).
Chip Enable (E0, E1, E2). These input signals
are used to set the value that is to be looked for on
the three least significant bits (b3, b2, b1) of the 7-
bit Device Select Code. These inputs must be tied
to VCC or VSS, to establish the Device Select
Code. When not connected (left floating), these in-
puts are read as Low (0,0,0).
Write Control (WC). This input signal is useful
for protecting the entire contents of the memory
from inadvertent write operations. Write opera-
tions are disabled to the entire memory array when
Write Control (WC) is driven High. When uncon-
nected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, Device
Select and Address bytes are acknowledged,
Data bytes are not acknowledged.
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Table 4. Most Significant Byte Table 5. Least Significant Byte
7/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
DEVICE OPERATION The device supports the I2 C protocol. This is sum-
marized in Figure 5.. Any device that sends data
on to the bus is defined to be a transmitter, and
any device that reads the data to be a receiver.
The device that controls the data transfer is known
as the bus master, and the other as the slave de-
vice. A data transfer can only be initiated by the
bus master, which will also provide the serial clock
for synchronization. The M24xxx-B device is al-
ways a slave in all communication.
Start ConditionStart is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop ConditionStop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Acknowledge Bit (ACK)The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During theth clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Data InputDuring data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory AddressingTo start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b.
Up to eight memory devices can be connected on
a single I2 C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the de-
vice only responds if the Chip Enable Address is
the same as the value on the Chip Enable (E0, E1,
E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
Table 6. Operating ModesNote:1. X = VIH or VIL.
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Write Operations Following a Start condition the bus master sends
a Device Select Code with the R/W bit (RW) reset
to 0. The device acknowledges this, as shown in
Figure 7., and waits for two address bytes. The de-
vice responds to each address byte with an ac-
knowledge bit, and then waits for the data byte.
Writing to the memory may be inhibited if Write
Control (WC) is driven High. Any Write instruction
with Write Control (WC) driven High (during a pe-
riod of time from the Start condition until the end of
the two address bytes) will not modify the memory
contents, and the accompanying data bytes are
not acknowledged, as shown in Figure 6..
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4.) is sent first, followed by the Least Signifi-
cant Byte (Table 5.). Bits b15 to b0 form the
address of the byte in memory.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
After the Stop condition, the delay tW, and the suc-
cessful completion of a Write operation, the de-
vice’s internal address counter is incremented
automatically, to point to the next byte address af-
ter the last one that was modified.
During the internal Write cycle, Serial Data (SDA)
is disabled internally, and the device does not re-
spond to any requests.
Byte WriteAfter the Device Select code and the address
bytes, the bus master sends one data byte. If the
addressed location is Write-protected, by Write
Control (WC) being driven High, the device replies
9/25
M24128-BW, M24128-BR, M24256-BW, M24256-BRwith NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-
ed, the device replies with Ack. The bus master
terminates the transfer by generating a Stop con-
dition, as shown in Figure 7..
Page WriteThe Page Write mode allows up to 64 bytes to be
written in a single Write cycle, provided that they
are all located in the same ’row’ in the memory:
that is, the most significant memory address bits,
b15-b6, are the same. If more bytes are sent than
will fit up to the end of the row, a condition known
as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implemen-
tation dependent way.
The bus master sends from 1 to 64 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If Write Control (WC) is
High, the contents of the addressed memory loca-
tion are not modified, and each data byte is fol-
lowed by a NoAck. After each byte is transferred,
the internal byte address counter (the 6 least sig-
nificant address bits only) is incremented. The
transfer is terminated by the bus master generat-
ing a Stop condition.
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Minimizing System Delays by Polling On ACKDuring the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (tw) is shown in Table
14. and Table 15., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 8., is: Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction). Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
11/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Read OperationsRead operations are performed independently of
the state of the Write Control (WC) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address ReadA dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 9.) but without sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
puts the contents of the addressed byte. The bus
master must not acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Current Address ReadFor the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the R/W bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 9., without acknowledging the
byte.
M24128-BW, M24128-BR, M24256-BW, M24256-BR
Sequential ReadThis operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9..
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read ModeFor all Read commands, the device waits, after
each byte read, for an acknowledgment during theth bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
INITIAL DELIVERY STATEThe device is delivered with all the memory array
bits set to 1 (each byte contains FFh).
13/25
M24128-BW, M24128-BR, M24256-BW, M24256-BR
MAXIMUM RATINGStressing the device outside the ratings listed in
Table 7. may cause permanent damage to the de-
vice. These are stress ratings only, and operation
of the device at these, or any other conditions out-
side those indicated in the Operating sections of
this specification, is not implied. Exposure to Ab-
solute Maximum Rating conditions for extended
periods may affect device reliability. Refer also to
the STMicroelectronics SURE Program and other
relevant quality documents.
Table 7. Absolute Maximum RatingsNote:1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)
