M2201 Fast Delivery |IC PHOENIX CO.,LIMITED

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M2201
2-Wires 1 Kbit (x8) Serial EEPROM
M2201
2-Wires 1 Kbit (x8) Serial EEPROM
July 1999 1/15
Figure 1. Logic Diagram
TWO WIRE SERIAL INTERFACE
100.000 ERASE/WRITE CYCLES with
100 YEARS DATA RETENTION at 55°C
SINGLE SUPPLY VOLTAGE: 4.5V to 5.5V for M2201 version 2.7V to 5.5V for M2201V version
HARDWARE WRITE CONTROL
100 KBIT TRANSFER RATE
BYTE WRITE
PAGE WRITE (up to 4 BYTES)
SELF TIMED PROGRAMMING CYCLE
AUTOMATIC ADDRESS INCREMENTING
ENHANCED ESD/LATCH UP
DESCRIPTION
The M2201 is a simplified 2-wire bus 1 Kbit electri-
cally erasable programmable memory (EEPROM),
organized as 128 x8 bits. It is manufactured in
STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees a data reten-
tion of 100 years at 55°C.
The M2201 is available in Plastic Dual-in-Line,
Plastic Small Outline and Thin Shrink Small Out-
line packages.
The memory is compatible with a two wire serial
interface which uses a bi-directional data bus and
serial clock. Read and write operations are initi-
ated by a START condition generated by the bus
master and ended by a STOP condition.
Address bits and RW bit are defined in one single
byte, instead of two (or three) bytes for the standard2 C protocol.
Table 1. Signal Names
When writing data to the memory, it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way. Data transfers are termi-
nated with a STOP condition.
Power On Reset: VCC lock out write protect. In
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Until the VCC
voltage has reached the POR threshold value, the
internal reset is active, all operations are disabled
and the device will not respond to any command.
In the same way, when VCC drops down from the
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable VCC
must be applied before applying any logic signal.
Figure 2A. DIP Pin Connections
Figure 2B. SO and TSSOP Pin Connections
DESCRIPTION (cont’d)
Notes:1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents. MIL-STD-883C, 3015.7 (100pF, 1500 Ω). EIAJ IC-121 (Condition C) (200pF, 0 Ω).
Table 2. Absolute Maximum Ratings (1)
Warning: NC = Not Connected. Warning: NC = Not Connected.
2/15
M2201
Figure 3. Maximum RL Value versus Bus Capacitance (CBUS)
SIGNAL DESCRIPTIONS
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to VCC
to act as a pull up (see Figure 3).
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to VCC to act as pull up (see Figure 3).
Write Control (WC). An hardware Write Control
feature (WC) is offered on pin 7. This feature is
usefull to protect the contents of the memory from
any erroneous erase/write cycle. The Write Control
signal is used to enable (WC = VIH) or disable (WC
= VIL) the internal write protection. When uncon-
nected, the WC input is internally read as VIL (WC
is disabled).
DEVICE OPERATION
The device that controls the data transfer is known
as the master. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The M2201 is always a slave device
in all communications.
Start Condition. START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the M2201 continu-
ously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition. STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the M2201 and the
bus master. A STOP condition at the end of a Read
command forces the standby state. A STOP condi-
tion at the end of a Write command triggers the
internal EEPROM write cycle.
Acknowledge Bit (ACK). An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input. During data input the M2201 sample
the SDA bus signal on the rising edge of the clock
SCL. Note that for correct device operation the SDA
signal must be stable during the clock low to high
transition and the data must change ONLY when
the SCL line is low.
3/15
M2201
Note: 1. The results come from simulation, actual results may vary. These figures are not guaranteed.
Table 3. Input Parameters (TA = 25 °C, f = 100 kHz )
Table 4. DC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
4/15
M2201
Notes:1. For a reSTART condition, or following a write cycle. The minimum value delays the falling/rising edge of SDA away from SCL = 1 in order to avoid unwanted START and/or STOP
conditions.
Table 5. AC Characteristics
(TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5V to 5.5V or 2.7V to 5.5V)
Memory Addressing. To start communication be-
tween the bus master and the slave M2201, the
master must initiate a START condition. Following
this, the master sends onto the SDA bus line 8 bits
(MSB first) corresponding to the 7th bit byte-ad-
dress and a READ or WRITE bit. This 8th bit is set
to ’1’ for read and ’0’ for write operations. If a match
is found, the corresponding memory will acknow-
ledge the identification on the SDA bus during the
9th bit time.
Write Operations
Following a START condition the master sends the
byte address with the RW bit reset to ’0’. The
memory acknowledges this and waits for a data
byte. Any write command with WC = 1 (during a
period of time from the START condition until the
end of the Byte Address) will not modify data and
will NOT be acknowledged on data bytes, as in
Figure 8.
Table 6. AC Measurement Conditions
Figure 4. AC Testing Input Output Waveforms
5/15
M2201
Figure 5. AC Waveforms
6/15
M2201
Figure 6. I2 C Bus Protocol
Byte Write. In the Byte Write mode the master
sends one data byte, which is acknowledged by the
memory. The master then terminates the transfer
by generating a STOP condition.
Page Write. The Page Write mode allows up to 4
bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the
memory: that is the 5 most significant memory
address bits (A6-A2) are the same. The master
sends from one up to four bytes of data, which are
each acknowledged by the memory. After each
byte is transfered, the internal byte address counter
(2 least significant bits only) is incremented. The
transfer is terminated by the master generating a
STOP condition. Care must be taken to avoid ad-
dress counter ’roll-over’ which could result in data
being overwritten.
It must be noticed that, for any write mode, the
generation by the master of the STOP condition
starts the internal memory program cycle. All inputs
are disabled until the completion of this cycle and
the memory will not respond to any request.
Minimizing System Delays by Polling On ACK.
During the internal write cycle, the memory discon-
nects itself from the bus in order to copy the data
from the internal latches to the memory cells. The
maximum value of the write time (tW) is given in the
AC Characteristics table, since the typical time is
shorter, the time seen by the system may be re-
7/15
M2201
Figure 7. Write Cycle Polling using ACK
duced by an ACK polling sequence issued by the
master. The sequence is as follows: Initial condition: a Write is in progress (see Fig-
ure 7). Step 1: the Master issues a START condition
followed by a Device Select byte (1st byte of
the new instruction).
DEVICE OPERATION (cont’d) – Step 2: if the memory is busy with the internal
write cycle, no ACK will be returned and the
master goes back to Step 1. If the memory
has terminated the internal write cycle, it will
respond with an ACK, indicating that the mem-
ory is ready to receive the second part of the
next instruction (the first byte of this instruc-
tion was already sent during Step 1).
8/15
M2201

Partno	Mfg	Dc	Qty	Available	Descript
M2201		N/a	2	avai	2-Wires 1 Kbit (x8) Serial EEPROM
M2201	ACER	N/a	17	avai	2-Wires 1 Kbit (x8) Serial EEPROM