LV86 ,Quad. 2-input Exclusive-OR Gatesapplications. The TRI-STATE en-recommendationables, EN, allow the device to be disabled when not in ..
LVC02A ,Quad 2-input NOR gateLOGIC DIAGRAM (ONE GATE)A2 1A1Y 13 1BY5 2A2Y 4 B6 2B8 3A3Y 10 SV008209 3B11 4A4Y 1312 4BFUNCTION TA ..
LVC06A , HEX INVERTER BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS
LVC08A ,Quad 2-input AND gatePIN CONFIGURATION LOGIC SYMBOL1A1A 1 14 1VCC 1Y31B21B 2 13 4B2A42Y1Y 3 12 4A62B52A 4 11 4Y3A93Y83B2 ..
LVC10A , TRIPLE 3-INPUT POSITIVE-NAND GATE
LVC11 ,Triple 3-input AND gatePIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC)1&2V1A 114 12CC131B 213 1C 3&4652A 3 12 1Y9&102B 4 11 3C81 ..
M30291FAVHP , RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30291FCVHP , RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
M30302FEPFP , SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30302MAP , SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M3045S , Schottky Barrier Rectifier
M30612E4FP , SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LV86
3V Enhanced CMOS Quad Differential Line Receiver
DS34LV86T Enhanced CMOS Quad Differential Line Receiver
General DescriptionThe DS34LV86Tisa high speed quad differential CMOSre-
ceiver that meetsthe requirementsof both TIA/EIA-422-B
and ITU-T V.11.The CMOS DS34LV86T features typicallow
staticICCof9mA which makesit idealfor battery powered
and power conscious applications. The TRI-STATE®en-
ables,EN, allow thedeviceto bedisabled whennot inuseto
minimize power consumption. The dual enable schemeal-
lowsfor flexibilityin turning receiversonandoff.
The receiver output (RO)is guaranteedtobe High whenthe
inputsareleft open.The receivercan detect signalsaslow ±200mV overthe common mode rangeof ±10V.There-
ceiver outputs (RO)are compatible with TTLand LVCMOS
levels.
Features Low power CMOS design(30 mW typical) Interoperable with existing5V RS-422 networks Industrial temperature range Meets TIA/EIA-422-B (RS-422)and ITU-T V.11
recommendation 3.3V Operation ±7V common mode rangeVID =3V ±10V common mode rangeVID= 0.2V Receiver OPEN input failsafe feature GuaranteedAC parameter:
Maximum Receiver Skew:4ns
Transition time: 10nsPin compatible with DS34C86T32 MHz Toggle Frequency 6.5k ESD Tolerance (HBM) Availablein SOIC packaging
Connection Diagram Truth Table
Enable Inputs Output RI+–RI− RO Z
HVID≥ +0.2V H
HVID≤ −0.2V L Open† H LogicLow= LogicHigh= Irrelevant= TRI-STATE= Open,Not Terminated
TRI-STATE®isa registeredtrademark ofNationalSemiconductorCorporation.
Dual-In-Line PackageDS012644-1
Top View
Order Number DS34LV86TN, DS34LV86TM
SeeNS Package Number M16Aor N16EFebruary 1997
DS34L
V86T
Enhanced
CMOS
Quad
Differential
Line
Receiver 1998 National Semiconductor Corporation DS012644
