LPC3180FEL320 ,16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interfacefeaturesn ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, runningat up to 2 ..
LPC3180FEL320 ,16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interfaceBlock diagramVFP9 ETB ETM9USB transceiver interfaceD-TCM I-TCM0 kB 0 kBARM9EJSD-CACHE I-CACHE32 kB ..
LPC3220FET296 ,ARM926EJ-S with 128 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controllerFeatures and benefits ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz. Vector Flo ..
LPC3230FET296 ,ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller, LCD controllerapplications. NXP achieved their performance goals using a 90 nanometer process to implement an ARM ..
LPC3250FET296 ,ARM926EJ-S with 256 kB SRAM, USB High-speed OTG, SD/MMC, NAND flash controller, Ethernet, LCD controller LPC3220/30/40/5016/32-bit ARM microcontrollers; hardware floating-point coprocessor, USB On-The-Go ..
LPC4045ATED100K , choke coil inductor
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LT1121IS8-5#PBF ,Micropower Low Dropout Regulators with Shutdown
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LPC3180FEL320
16/32-bit ARM microcontroller; hardware floating-point coprocessor, USB On-The-Go, and SDRAM memory interface
General descriptionThe LPC3180 is an ARM9-based microcontroller for embedded applications requiring
high performance combined with low power dissipation. It achieves these objectives
through the combination of NXP’s state-of-the-art 90 nanometer technology with an
ARM926EJ-S CPU core witha Vector Floating Point (VFP) coprocessor anda large array
of standard peripherals including USB On-The-Go.
The microcontroller can operate at over 200 MHz CPU frequency (about 220 MIPS per
ARM Inc.). The ARM926EJ-S CPU incorporates a 5-stage pipeline and has a Harvard
architecture with separate 32 kB instruction and data caches, a demand paged MMU,
DSP instruction extensions witha single cycle MAC, and Jazelle Java bytecode execution
hardware. A block diagram of the microcontroller is shown in Figure1.
Power optimization in this microcontroller is done through process and technology
development (Intrinsic Power), and architectural means (Managed Power).
The LPC3180 also incorporates an SDRAM interface, NAND flash interfaces, USB 2.0
full-speed interface, seven UARTs, twoI2 C-bus interfaces, two SPI ports,a Secure Digital
(SD) interface, and a 10-bit ADC in addition to many other features.
Features
2.1 Key features ARM926EJ-S processor with 32 kB instruction cache and 32 kB data cache, running
at up to 208 MHz. 64 kB of SRAM. High-performance multi-layer AHB bus system provides a separate bus for CPU data
and instruction fetch, two data buses for the DMA controller, and another for the USB
controller. External memory interfaces: one supports DDR and SDR SDRAM, another supports
single-level and multi-level NAND flash devices and can serve as an 8-bit parallel
interface. General purpose DMA controller that canbe used with the SD card and SPI interfaces,
as well as for memory-to-memory transfers. USB 2.0 full-speed device, host (OHCI compliant), and OTG block. A dedicated PLL
provides the 48 MHz USB clock. Multiple serial interfaces, including seven UARTs, two SPI controllers, and two single
master I2 C-bus interfaces. SD memory card interface.
LPC3180
16/32-bit ARM microcontroller; hardware floating-point
coprocessor, USB On-The-Go, and SDRAM memory interface
Rev. 02 — 15 February 2007 Preliminary data sheet
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface Upto55 GPI, GPO, and GPIO pins. Includes12 GPI pins,24 GPO pins, andsix GPIO
pins. 10-bit ADC with input multiplexing from three pins. Real-Time Clock (RTC) with separate power supply and power domain, clocked by a
dedicated 32 kHz oscillator. Includes a 128 byte scratch pad memory. The RTC may
remain active when the rest of the chip is not powered. 32-bit general purpose high-speed timer with 16-bit pre-scaler with capture and
compare capability. 32-bit millisecond timer driven from the RTC clock. Interrupts maybe generated using
two match registers. Watchdog timer. Two PWM blocks with an output rate up to 50 kHz. Keyboard scanner function provides automatic scanning of up to an 8× 8 key matrix. Standard ARM test/debug interface for compatibility with existing tools. Emulation trace buffer with 2k× 24-bit RAM allows trace via JTAG. On-chip crystal oscillator. Stop mode saves power, while allowing many peripheral functions to restart CPU
activity. On-chip PLL allows CPU operation up to the maximum CPU rate without the need for
a high frequency crystal. Boundary scan for simplified board testing.
Ordering information[1] F = −40 °C to +85 °C temperature range.
Table 1. Ordering informationLPC3180FEL320[1] LFBGA320 plastic low profile fine-pitch ball grid array
package; 320 balls; body 13 × 13 × 0.9 mm
SOT824-1
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface Block diagram
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface Pinning information
5.1 Pinning
Table 2. Pin allocation table
Row A
Row B
Row C
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface
Row D
Row E
Row F
Row G
Row H
Row J
Row K
Row L
Table 2. Pin allocation table …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface
Row M
Row N
Row P
Row R
Row T
Row U
Row V
Row W
Row Y
Row AA
Row AB
Table 2. Pin allocation table …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface[1] These pins are connected internally and must be left unconnected in an application.
Row AC
Row AD
Table 2. Pin allocation table …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface
5.2 Pin description
Table 3. Pin descriptionADIN0 C24 I input 0 to the ADC
ADIN1 E22 I input 1 to the ADC
ADIN2 D23 I input 2 to the ADC
FLASH_ALE AA16 O address latch enable for NAND flash
FLASH_CE_N AC21 O chip enable for NAND flash
FLASH_CLE AC15 O command latch enable for NAND flash
FLASH_IO[07:00] AD18, AC17, AD19,
AB19, AC20, AC19,
AD20, AD21
I/O NAND flash data bus
FLASH_RD_N AA17 O read strobe for NAND flash
FLASH_RDY AC18 I ready status from NAND flash
FLASH_WR_N AD17 O write strobe for NAND flash
GPI_00 H1 I general purpose input 00
GPI_01/
SERVICE_N I
GPI_01 — general purpose input 01
SERVICE_N — boot select input
GPI_02 J3 I general purpose input 02
GPI_03 AA11 I general purpose input 03
GPI_04/
SPI1_BUSY I
GPI_04 — general purpose input 04
SPI1_BUSY — busy input for SPI1
GPI_05 A12 I general purpose input 05
GPI_06/
HSTIM_CAP
AA3 I
GPI_06 — general purpose input 06
HSTIM_CAP — capture input trigger for the high-speed timer
GPI_07 J1 I general purpose input 07
GPI_08/
KEY_COL6/
SPI2_BUSY I
GPI_08 — general purpose input 08
KEY_COL6 — keyboard scan column input 6
SPI2_BUSY — busy input for SPI2
GPI_09/
KEY_COL7 I
GPI_09 — general purpose input 09
KEY_COL7 — keyboard scan column input 7
GPI_10/
U4_RX I
GPI_10 — general purpose input 10
U4_RX — UART 4 receive data input
GPI_11 D10 I general purpose input 11
GPIO_00 T3 I/O general purpose input/output 00
GPIO_01 R1 I/O general purpose input/output 01
GPIO_02/
KEY_ROW6 I/O
GPIO_02 — general purpose input/output 02
KEY_ROW6 — keyboard scan row output 6
GPIO_03/
KEY_ROW7 I/O
GPIO_03 — general purpose input/output 03
KEY_ROW7 — keyboard scan row output 7
GPIO_04 T2 I/O general purpose input/output 04
GPIO_05 R2 I/O general purpose input/output 05
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfaceGPO_00/
TST_CLK1
AB9 O
GPO_00 — general purpose output 00
TST_CLK1 — Clock test output 1, controlled by the TEST_CLK
register
GPO_01 AC9 O general purpose output 01
GPO_02 L4 O general purpose output 02
GPO_03 L1 O general purpose output 03
GPO_04 Y3 O general purpose output 04
GPO_05 AB10 O general purpose output 05
GPO_06 M4 O general purpose output 06
GPO_07 M3 O general purpose output 07
GPO_08 M1 O general purpose output 08
GPO_09 N4 O general purpose output 09
GPO_10 M2 O general purpose output 10
GPO_11 AB1 O general purpose output 11
GPO_12 P3 O general purpose output 12
GPO_13 N1 O general purpose output 13
GPO_14 AD9 O general purpose output 14
GPO_15 R4 O general purpose output 15
GPO_16 N2 O general purpose output 16
GPO_17 B12 O general purpose output 17
GPO_18 P1 O general purpose output 18
GPO_19 AC10 O general purpose output 19
GPO_20 AD10 O general purpose output 20
GPO_21/
U4_TX O
GPO_21 — general purpose output 21
U4_TX — UART 4 transmit data output
GPO_22/
U7_HRTS O
GPO_22 — general purpose output 22
U7_HRTS — UART 7 hardware flow control (RTS) output
GPO_23/
U2_HRTS
A11 O
GPO_23 — general purpose output 23
U2_HRTS — UART 2 hardware flow control (RTS) output
HIGHCORE A3 O core voltage select output
I2C1_SCL Y4 I/O serial clock for I2C1
I2C1_SDA AC1 I/O serial data for I2C1
I2C2_SCL AD8 I/O serial clock for I2C2
I2C2_SDA AA9 I/O serial data for I2C2
JTAG1_NTRST D7 I JTAG reset input
JTAG1_RTCK A6 O JTAG return clock output
JTAG1_TCK B5 I JTAG clock input
JTAG1_TDI B6 I JTAG data input
JTAG1_TDO A4 O JTAG data output
JTAG1_TMS A5 I JTAG test mode select input
Table 3. Pin description …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfaceKEY_COL0 to
KEY_COL5
D2, F4, C1, C2, E4, keyboard scan column inputs
KEY_ROW0 to
KEY_ROW5
G3, F2, E1, F3, D1, keyboard scan row outputs 0 through 5
MS_BS Y1 I/O SD card command input/output (SD_CMD)
MS_DIO0 to MS_DIO3 W2, U2, Y2, V4 I/O SD card data bus (SD_D0 to SD_D3)
MS_SCLK AA1 O SD card clock output (SD_CLK)
ONSW D12 O VCCon output signal
PLL397_LOOP C21 I/O loop filterpinfor PLL397; requires external componentsif PLL397
is used
PWM_OUT1 J2 O output of Pulse Width Modulator 1
PWM_OUT2 H3 O output of Pulse Width Modulator 2
RAM_A[14:00] W21, AA24, Y23,
AB24, Y22, AA23,
AB23, AB22, AC23,
AA21, AC22, AD24,
AD23, AB20, AD22 SDRAM address bus, pins 14 to 00
RAM_CAS_N V23 O SDRAM column address strobe output
RAM_CKE U24 O SDRAM clock enable output
RAM_CLK U23 O SDRAM clock output
RAM_CLKIN T21 I SDRAM clock return input
RAM_CS_N V24 O SDRAM chip select output
RAM_D[15:00] L24, M23, L22,
M24, N23, M22,
N24, P23, N21,
P24, R23, P21,
R24, T24, T22, T23
I/O SDRAM data bus, pins 15 to 00
RAM_D[16]/
DDR_DQS0
L23 I/O
RAM_D[16] — SDRAM data bus, pin 16
DDR_DQS0 — SDRAM data strobe output for lower byte
RAM_D[17]/
DDR_DQS1
L21 I/O
RAM_D[17] — SDRAM data bus, pin 17
DDR_DQS1 — SDRAM data strobe output for upper byte
RAM_D[18]/
DDR_NCLK
K24 I/O
RAM_D[18] — SDRAM data bus, pin 18
DDR_NCLK — inverted SDRAM clock output for DDR
RAM_D[31:19]/
PIO_SD[12:00]
E24, E23, F21, F24,
G24, H23, J21,
G23, H22, K23,
H24, J24, H21
I/O
RAM_D[31:19] — SDRAM data bus, pins 31 to 19
I/O
PIO_SD[12:00] — general purpose input/output, pins 12 to 00;
details may be found in Section 6.10 “General purpose parallel
I/O” on page 18
RAM_DQM[3:0] W24, V21, W23,
Y24 SDRAM byte write mask outputs
RAM_RAS_N U21 O SDRAM row address strobe output
RAM_WR_N V22 O SDRAM write strobe output
RESET_N D13 I system reset input
RESOUT_N AB12 O reset output signal
RTCX_IN A14 I RTC oscillator input
RTCX_OUT A13 O RTC oscillator output
Table 3. Pin description …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfaceSPI1_CLK W3 O clock output for SPI1
SPI1_DATIN V1 I data input for SPI1
SPI1_DATIO W1 I/O data input/output for SPI1
SPI2_CLK V3 O clock output for SPI2
SPI2_DATIN T4 I data input for SPI2
SPI2_DATIO V2 I/O data input/output for SPI2
SYSCLKEN C5 I/O system clock request
SYSX_IN A23 I main oscillator input
SYSX_OUT B23 O main oscillator output
TEST D3 I test input; internally pulled down, should be left floating in an
application
TST_CLK2 AB3 O clock test output 2, controlled by the TEST_CLK
U1_RX/
PIO_INP[15] I
U1_RX — UART 1 receive data input
PIO_INP[15] — general purpose input to PIO_INP_STATE
register
U1_TX B10 O UART 1 transmit data output
U2_HCTS/
PIO_INP[16] I
U2_HCTS — UART 2 hardware flow control (CTS) input
PIO_INP[16] — general purpose input to PIO_INP_STATE
register
U2_RX/
PIO_INP[17] I
U2_RX — UART 2 receive data input
PIO_INP[17] — general purpose input to PIO_INP_STATE
register
U2_TX D9 O UART 2 transmit data output
U3_RX/
PIO_INP[18] I
U3_RX — UART 3 receive data input
PIO_INP[18] — general purpose input to PIO_INP_STATE
register
U3_TX A7 O UART 3 transmit data output
U5_RX/PIO_INP[20] A2 I
U5_RX — UART 5 receive data input
PIO_INP[20] — general purpose input to PIO_INP_STATE
register
U5_TX C4 O UART 5 transmit data output
U6_IRRX/
PIO_INP[21] I/O
U6_IRRX — UART 6 receive data input; can be IrDA data
PIO_INP[21] — general purpose input to PIO_INP_STATE
register
U6_IRTX D5 O UART 6 transmit data output; can be IrDA data
U7_HCTS/
PIO_INP[22] I
U7_HCTS — UART 7 hardware flow control (CTS) input
PIO_INP[22] — general purpose input to PIO_INP_STATE
register
U7_RX/
PIO_INP[23] I
U7_RX — UART 7 receive data input
PIO_INP[23] — general purpose input to PIO_INP_STATE
register
U7_TX B3 O UART 7 transmit data output
USB_ATX_INT_N AA7 I USB interrupt from external transceiver
Table 3. Pin description …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfaceUSB_DAT_VP/
U5_RX
AA8 I/O
USB_DAT_VP — USB transmit data
U5_RX — UART 5 receive data input
USB_I2C_SCL AC8 I/O serial clock for USB I2 C-bus
USB_I2C_SDA AD7 I/O serial data for USB I2 C-bus
USB_OE_TP_N AD6 I/O USB transmit enable for DAT/SE0
USB_SE0_VM/
U5_TX
AB7 I/O
USB_SE0_VM — USB single ended zero transmit
U5_TX — UART 5 transmit data output
VDD12 B14, A21, B19 I 1.2 V power supply for various internal functional blocks that are
not included with VDD_CORE or VDD_COREFXD
VDD_AD28 D24, E21 I 3.0 V power supply and positive reference voltage for the ADC
VDD_CORE12_01 to
VDD_CORE12_03,
VDD_CORE12_05 to
VDD_CORE12_08
AA2, D6, K21, L3,
AA12, AB6, AB18 1.2 V core main power supply for the CPU and other core logic;
this voltage may be reduced to 0.9 V when the core is running at
or below 13 MHz; the HIGHCORE pin may be used to signal this
condition to an external voltage switch
VDD_COREFXD12_01,
VDD_COREFXD12_02
C10, D18 I 1.2V core secondary power supply voltageforthe CPU and other
core logic; this supply cannot be reduced in the same manner as
the VDD_CORE12 supply
VDD1828,
VDD_IO1828_01,
VDD_IO1828_02
AD4, AA4, B7, B4 I 1.8 V or 3.0 V power supply for I/O pins that may operate from
either a 1.8 V range or a 3 V range
VDD_IO18_01 to
VDD_IO18_04
AA19, AA15, AB11,
AC7 1.8 V power supply for I/O pins that operate only from a 1.8V
range
VDD28, VDD_IO28_01,
VDD_IO28_02
U4, G4, D14, A16,
A17, C17, A19 3.0 V power supply for I/O pins that operate only from a 3 V range
VDD_OSC12 D20 I 1.2 V power supply for the main oscillator
VDD_PLL397_12 C22 I 1.2 V power supply for the 397x PLL
VDD_PLLHCLK_12 A22 I 1.2 V power supply for the HCLK PLL
VDD_PLLUSB_12 B22 I 1.2 V power supply for the USB PLL
VDD_RTC12 C12 I 1.2 V power supply for the RTC block
VDD_RTCCORE12 C11 I 1.2 V power supply for the RTC block
VDD_RTCOSC12 C14 I 1.2 V power supply for the 32 kHz RTC oscillator
VDD_SDRAM18_01 to
VDD_SDRAM18_09
G21, F22, J22, K22,
P22, U22, Y21,
AC24, AA20 1.8 V power supply for the SDRAM controller block
VSS B16, D15, AC11,
AB2, AD1, AC2,
AD5, AC5, AA6,
AC6, AD3, AC4,
AC3, AB4, AD11,
C9, A9, A8, C8,
D11,B11, B15, A15,
AB5, W4, C16, D17,
A20, C19 ground for various internal logic blocks that are not included with
VDD_CORE or VDD_COREFXD.
VSS_AD D22 I groundfor the ADC; this should nominallybe the same voltageas
VSS, but should be isolated to minimize noise and conversion
error
Table 3. Pin description …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfaceVSS_CORE_01 to
VSS_CORE_09
C20, D8, D16, J4,
R3, R21, AA5,
AA10, AB17 ground for the core logic functions
VSS_IO1828_01 to
VSS_IO1828_02
D4, A10 I groundforI/O pins that may operate from eithera 1.8V rangeora V range
VSS_IO18_01 to
VSS_IO18_04
AC16, AD15, AC12,
AB8 ground for I/O pins that operate only from a 1.8 V range
VSS_IO28_01 to
VSS_IO28_03
E3, F1, N3 I ground for I/O pins that operate only from a 3 V range
VSS_OSC B21 I ground for the main oscillator
VSS_PLL397 C23 I ground for the 397x PLL
VSS_PLLHCLK D19 I ground for the HCLK PLL
VSS_PLLUSB B20 I ground for the USB PLL
VSS_RTCCORE B13 I ground for the RTC block
VSS_RTCOSC C13 I ground for the 32 kHz RTC oscillator
VSS_SDRAM_01 to
VSS_SDRAM_10
F23,G22, J23,M21,
N22, R22, W22,
AA22, AB21, AA18 ground for the SDRAM controller block
i.c. A18, B17, B18,C18,
U1, AD2, AA13,
AD16, AB16, AA14,
AC14, AB15, AD14,
AC13, AB14, AD13,
AB13, AD12, H2,
G1, G2, H4, D21,
B24, A24, C15
internally connected; leave open
Table 3. Pin description …continued
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface Functional description
6.1 Architectural overviewThe microcontroller is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on RISC
principles, and the instruction set and related decode mechanism are much simpler than
those of microprogrammed CISCs. This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
A 5-stage pipeline is employed so that all parts of the processing and memory systems
can operate continuously. At any one point in time, several operations are typically in
progress: subsequent instruction fetch, next instruction decode, instruction execution,
memory access, and write-back. The combination of architectural enhancements gives
the ARM9 about 30 % better performance than an ARM7 running at the same clock rate:
Approximately 1.3 clocks per instruction (1.9 clocks per instruction for ARM7).
Approximately 1.1 Dhrystone MIPS/MHz (0.9 Dhrystone MIPS/MHz for ARM7).
The ARM926EJ-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM926EJ-S processor has two instruction sets: The standard 32-bit ARM set. A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
In addition, the ARM9 includes enhanced DSP instructions and multiplier, as well as an
enhanced 32-bit MAC block.
6.2 Vector Floating Point (VFP) coprocessorThis CPU coprocessor provides full supportfor single-precision and double-precision add,
subtract, multiply, divide, and multiply-accumulate operations at CPU clock speeds. It is
compliant with the IEEE 754 standard, and enables advanced Motor control and DSP
applications. The VFP has three separate pipelines for floating-point MAC operations,
divide or square root operations, and load/store operations. These pipelines can operate
in parallel and can complete execution out of order. All single-precision instructions,
except divide and square root, take one cycle and double-precision multiply and
multiply-accumulate instructions take two cycles. The VFP also provides format
conversions between floating-point and integer word formats.
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface
6.3 AHB matrixThe microcontroller has a multi-layer AHB matrix for inter-block communication. AHB is
the ARM high-speed bus, which is part of the ARM bus architecture. AHB is a
high-bandwidth low-latency bus that supports multi-master arbitration and a bus
grant/request mechanism. For systems where there is only one bus master (the CPU), or
where there are two masters (CPU and DMA) and the CPU does not generally need to
contend with the DMA for program memory access (because the CPU has access to
memory on its local bus or has caches or another AHB bus etc.), this arrangement works
well. However, if there are multiple bus masters and the CPU needs access to external
memory,a single AHB bus can causea bottleneck. ARM’s solutionto this wasto inventa
multi-layer AHB which replaces the request/grant and arbitration mechanism with a
multiplexer fabric that pushes arbitration to the level of the devices. Thus, if a CPU and a
DMA controller want access to the same memory, the multi-layer fabric will arbitrate
between the two on granting access to that memory. This allows simultaneous access by
bus masters to different resources at the cost of increased arbitration complexity. As with
all trade-offs, the pros and cons must be analyzed, for a microcontroller operating at
200 MHz, removing guaranteed central arbitration in case more than one bus master is
active in favor of occasional local arbitration gives better performance.
The blocks outside the CPU can be roughly split into memory controllers, serial
communication, I/O, timers/counters and RTC, system control, and debug and trace
blocks. These are described as follows.
6.4 On-chip SRAMOn-chip SRAM may be used for code and/or data storage. The SRAM may be accessed
as 8/16/32 bit. The LPC3180 provides 64 kB of SRAM.
6.5 Memory mapThe LPC3180 memory map incorporates several distinct regions, as shown in Figure3.
Whenan applicationis running, the CPU interrupt vectors are re-mappedto allow themto
reside in on-chip SRAM.
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interface
6.6 SDRAM memory controllerThe SDRAM memory controller provides an interface between the system bus and
external (off-chip) memory devices.A single chip selectis supplied, supporting one group
of SDRAM in the same address range. The SDRAM controller supports SDR SDRAM
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfacedevices of 64/128/256/512/1024 Mbit in size, as well as DDR SDRAM devices of
64/128/256/512/1024 Mbit in size. The SDRAM controller uses four data ports to allow
simultaneous requests from multiple on-chip AHB bus masters.
6.7 NAND flash controllersThe LPC3180 includes two NAND flash controllers, onefor multi-level NAND flash devices
and one for single-level NAND flash devices. The two NAND flash controllers use the
same pinsto interfaceto external NAND flash devices,so only one interfaceis activeata
time.
6.7.1 Multi-Level Cell (MLC) NAND flash controllerThe MLC NAND flash controller interfaces to either multi-level or single-level NAND flash
devices. An external NAND flash device is used to allow the bootloader to automatically
load a portion of the application code into internal SRAM for execution following reset.
The MLC NAND flash controller supports up to 2 Gbit devices with small (528 byte) or
large (2114 byte) pages. Programmable NAND timing parameters allow support for a
variety of NAND flash devices. A built-in Reed-Solomon encoder/decoder provides error
detection and correction capability. A 528 byte data buffer reduces the need for CPU
supervision during loading. The MLC NAND flash controller also provides DMA support.
6.7.2 Single-Level Cell (SLC) NAND flash controllerThe SLC NAND flash controller interfacesto single-level NAND flash devicesupto2 Gbit size. DMA page transfers are supported, includinga20 byte DMA read and write FIFO.
Hardware support for ECC (Error Checking and Correction) is included for the main data
area. Software can correct a single bit error.
6.8 DMA controllerThe DMA controller allows peripheral-to memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receives. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the same AHB master or one area by each master.
The DMA controls eight DMA channels with hardware prioritization. The DMA controller
interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width.
DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either
big-endian or little-endian. Incrementing or non-incrementing addressing for source and
destination are supported, as well as programmable DMA burst size. Scatter or gather
DMA is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas of memory.
6.9 Interrupt controllerThe interrupt controlleris comprisedof three basic interrupt controller blocks, supportinga
total of 60 interrupt sources. Each interrupt source can be individually enabled/disabled
and configured for high or low level triggering, or rising or falling edge triggering. Each
interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt
NXP Semiconductors LPC3180
16/32-bit ARM microcontroller with external memory interfacestatus and masked interrupt status registers allow versatile condition evaluation. In
addition to peripheral functions, each of the six general purpose input/output pins and general purpose input pins are connected directly to the interrupt controller.
6.10 General purpose parallel I/OSome device pins that are not dedicated to a specific peripheral function have been
designed to be general purpose inputs, outputs, or I/Os. Also, some pins may be
configured either as a specific peripheral function or a general purpose input, output, or
I/O. A total of 55 pins can potentially be used as general purpose input/outputs, general
purpose outputs, and general purpose inputs.
GPIO pins may be dynamically configured as inputs or outputs. Separate registers allow
setting or clearing any number of GPIO and GPO outputs controlled by that register
simultaneously. The valueof the output registerfor standard GPIOs and GPO pins maybe
read back, as well as the current actual state of the port pins.
There are 12 GPI, 24 GPO, and six GPIO pins. When the SDRAM bus is configured for data bits, 13 of the remaining SDRAM data pins may be used as GPIOs.
6.10.1 Features Bit-level set and clear registers allowa single instruction setor clearof any numberof
bits in one port.
A single register selects direction for pins that support both input and output modes.
Direction control of individual bits.
For input/output pins, both the programmed output state and the actual pin state can
be read.
There are a total of 12 general purpose inputs, 24 general purpose outputs, and six
general purpose input/outputs.
Additionally, 13 SDRAM data lines may be used as GPIOs if a 16-bit SDRAM
interface is used (rather than a 32-bit interface).
6.11 10-bit ADCThe ADC is a three channel, 10-bit successive approximation ADC. The ADC may be
configuredto produce results witha resolution anywhere from10 bitsto3 bits. When high
resolutionis not needed, lowering the resolution can substantially reduce conversion time.
The analog portion of the ADC has its own power supply to enhance the low noise
characteristicsof the converter. This voltageis only supplied internally when the core has
voltage. However, the ADC block is not affected by any difference in ramp-up time for
VDD_AD and VDD_CORE voltage supplies.
6.11.1 Features Measurement range of 0 V to VDD_AD28 (nominally 3 V).
Low noise ADC.
Maximum 10-bit resolution, resolution can be reduced to any amount down to 3 bits
for faster conversion.
Three input channels.
