LNBP21PD ,LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACELNBP21LNBP SUPPLY AND CONTROL IC WITH2STEP-UP CONVERTER AND I C INTERFACE■ COMPLETE INTERFACE BETWE ..
LNBP21PD-TR ,LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Input Voltage16 VCCV DC Input Voltage 25 VU ..
LNBP21PD-TR ,LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
LNBP21PD-TR ,LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional o ..
LNBP8 ,LNB SUPPLY AND CONTROL VOLTAGE REGULATORLNBP8LNBP9LNB SUPPLY AND CONTROL VOLTAGE REGULATOR
LNBP21D2-TR-LNBP21PD-LNBP21PD-TR
LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
1/20October 2002 COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED STANDARDS FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC CABLE LENGTH DIGITAL COMPENSATION INTERNAL OVER TEMPERATURE
PROTECTION ESD RATING 4KV ON POWER
INPUT-OUTPUT PINS
DESCRIPTIONIntended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBP21isa
monolithic voltage regulator and interface IC,
assembled in SO-20 and PowerSO-20,
specifically designedto provide the power and the
13/18V, 22KHz tone signalling to the LNB
LNBP21LNBP SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER ANDI2C INTERFACE
SCHEMATIC DIAGRAM
LNBP212/20
downconverterin the antennaorto the multiswitch
box.In this application field,it offersa complete
solution with extremely low component count, low
power dissipation together with simple design and2 CTM standard interfac-ing.
This IC hasa builtin DC/DC step-up controller
that, froma single supply source ranging from8to
15V, generates the voltages that let the linear
post-regulatorto workata minimum dissipated
power. An UnderVoltage Lockout circuit will
disable the whole circuit when the supplied VCC
drops belowa fixed threshold (6.7V typically). The
internal 22KHz tone generatoris factory trimmed accordance to the standards, and can be
controlled either by theI2CTM interfaceor bya
dedicated pin (DSQIN) that allows immediate
DiSEqCTM data encoding (*).All the functionsof
thisIC are controlled viaI2CTM busby writing6
bits on the System Register (SR,8 bits). The
same register canbe read back, and two bits will
report the diagnostic status. When theICis putin
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pinsis closed, thus leavingall LNB
powering and control functionsto the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlledto be 13or 18V (typ.)by meanof the
VSELbit (Voltage SELect) for remote controlling non-DiSEqC LNBs. Additionally,itis possible increment by 1V (typ.) the selected voltage
valueto compensate for the excess voltage drop
along the coaxial cable (LLCbit HIGH).In orderto
minimise the power dissipation, the output voltage the internal step-up converteris adjustedto
allow the linear regulator to workat minimum
dropout. Anotherbitof the SRis addressedto the
remote controlof non-DiSEqC LNBs: the TEN
(Tone ENable) bit. Whenitis set to HIGH,a
continuous 22KHz toneis generated regardless the DSQIN pin logic status. The TEN bit must set LOW when theDSQIN pinis usedfor
DiSEqCTM encoding. The fully bi-directional
DiSEqCTM interfacingis completedby the built-in
22KHz tone detector.Its input pin (DETIN) must AC coupledto the DiSEqCTM bus, and the
extractedPWK data areavailableonthe
DSQOUT pin (*). orderto improve design flexibility andto allow
implementationof newcoming LNB remote control
standards, an analogic modulation input pinis
available (EXTM). An appropriate DC blocking
capaci-tor mustbe usedto couple the modulating
signal sourceto the EXTM pin. When external
modulationis not used, the relevant pin canbe left
open.
The current limitation block has two thresholds
that canbe selectedby the ISEL bitofthe SR;the
lower thresholdis between 400 and 550mA SEL =HIGH), while the higher threshold is
between 500 and 650mA(I SEL =LOW).
The current protection blockis SOA type. This
limits the short circuit current (Isc) typicallyat
200mA withI SEL =HIGH and at 300mA with
ISEL=LOW when the output portis connectedto
ground.is possible to set the Short Circuit Current
protection either statically (simple current clamp) dy-namically by the PCLbitof the SR; when
the PCL (Pulsed Current Limiting) bitis setto
LOW, the overcurrent protection circuit works
dynamically:as soonasan overloadis detected,
the outputis shut-down fora time toff, typically
900ms. Simultaneously the OLFbitof the System
Registeris set to HIGH. After this time has
elapsed, the outputis resumed fora timeton=1/
10toff (typ.).At the endof ton,if the overloadis still
detected, the protection circuit will cycle again
through Toff and Ton. At the endofa full Tonin
whichno overloadis detected, normal operationis
resumed and the OLFbitis resetto LOW. Typical
Ton+Toff timeis 990ms anditis determinedbyan
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on startin most conditions (**).
However, there could be some casesin whichan
highly capacitive load on the output may causea
difficult start-up when the dynamic protectionis
chosen. This canbe solvedby initiating any power
start-upin static mode (PCL=HIGH) and then
switchingto the dynamic mode (PCL=LOW) after chosen amountof time. Whenin static mode,
the OLFbit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload conditionis cleared.
This ICis also protected against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switchis
opened, and the OTFbitof the SRis setto HIGH.
Normal operationis resumed and the OTF bitis
resetto LOW when the junctionis cooled downto
140°C (typ.).
(*): External components areneededto complyto bi-directional DiSEqCTM bus hardware require-ments.Full complianceofthe wholeappli-
cationto DiSEqCTM specificationsisnot impliedbytheuseofthisIC.
(**): The current limitation circuithasno effectonthe loop-through switch. WhenENbitis LOW,the current flowing from LT1toLT2 must externally limited.
LNBP213/20
ORDERING CODES
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under these conditionis
not implied.
THERMAL DATA
PIN CONFIGUARATION (top view)
LNBP214/20
TABLEA: PIN CONFIGURATIONS
LNBP215/20
TYPICAL APPLICATION CIRCUIT(*)Setto GNDifnot used
(**) filtertobe used accordingto EUTELSAT reccomendationto implementthe DiSEqCTM2.x,not neededif bidirectional DiSEqCTM2.xis
not implemented (see DiSEqC implementation note)
(***) IC2isa STFettky,STS4DNFS30L,that includesboththe schottky diodeand theN-Channel Mos-Fet, needed forthe DC/DC converter,a So-8 package.Itcanbe replacedbya schottky diode (STPS2L3Aor similar)anda N-Channel Mos-Fet (STN4NF03Lor similar)
2C BUS INTERFACEData transmission from main μPto the LNBP21
and viceversa takes place through the2 wires I2C
bus interface, consistingof the two lines SDA and
SCL (pull-up resistorsto positive supply voltage
mustbe externally connected).
DATA VALIDITY shownin fig.1, the dataon the SDA line must stable during the high periodof the clock. The
HIGH and LOW stateof the data line can only
change when the clock signalon the SCL lineis
LOW.
START AND STOP CONDITIONS shownin fig.2a start conditionisa HIGHto
LOW transitionof the SDA line while SCLis HIGH.
The stop conditionisa LOWto HIGH transitionof
the SDA line while SCL is HIGH.A STOP
condi-tions must be sent before each START
condition.
BYTE FORMAT
Every byte transferredto the SDA line must
contain8 bits. Each byte mustbe followedby an
ac-knowledge bit. The MSBis transferred first.
ACKNOWLEDGE
The master (μP) putsa resistive HIGH levelon the
SDA line during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBP21) that
acknowledges hasto pull-down (LOW) the SDA
line during the acknowledge clock pulse,so that
the SDA lineis stable LOW during this clock pulse.
The peripheral which has been addressed hasto
generate an acknowledge after the receptionof
each byte, other-wise the SDA line remainsat the
HIGH level during the ninth clock pulse time.In
this case the master transmitter can generate the
STOP informationin orderto abort the transfer.
The LNBP21 won't gen-erate the acknowledgeif
the Vcc supplyis below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBP21, the μP can usea simpler transmission:
simplyit waits one clock without checking the
slave acknowledging, and sends the new data.
This approachof courseis less protected from
misworking and decreases the noise immunity.
LNBP216/20
Figure1: DATA VALIDITY ON THEI2 CBUS
Figure2: TIMING DIAGRAM ONI2 CBUS
Figure3: ACKNOWLEDGE ONI2 CBUS
LNBP217/20
LNBP1 SOFTWARE DESCRIPTIONINTERFACE PROTOCOL
The interface protocol comprises:A start condition (S)A chip address byte= hex10/11 (the LSBbit
determines read(=1)/write(=0) transmission)A sequenceof data(1 byte+ acknowledge)A stop condition (P)
ACK= Acknowledge Start Stop
R/W= Read/Write
SYSTEM REGISTER (SR,1 BYTE)
R,W= read and writebit Read-onlybit
Allbits resetto0at Power-On
TRANSMITTED DATA(I2 CBUS WRITE MODE)
When the R/Wbitin the chip addressis setto0,
the main μP can write on the System Register
(SR)of the LNBP21 viaI2C bus. Only6 bits outof
the8 available canbe writtenby the μP, since the
re-maining2 are leftto the diagnostic flags, and
are read-only. don't care.
Valuesare typical unless otherwise specified
RECEIVED DATA(I2C bus READ MODE)
The LNBP21 can provideto the Mastera copyof
the SYSTEM REGISTER information via I2C bus read mode. The read modeis Master activated sending the chip address with R/Wbit setto1. the following master generated clocks bits, the
LNBP21 issuesa byte on the SDA data bus line
(MSB transmitted first). the ninth clockbit the MCU master can: acknowledge the reception, startingin this way
the transmission of another byte from the
LNBP21;
LNBP218/20 no acknowledge, stopping the read mode
communication.
While the whole registeris read back by the μP,
only the two read-only bits OLF and OTF convey
di-agnostic informations about the LNBP21.
Valuesare typical unless otherwise specified
POWER-ON I2C INTERFACE RESET
TheI2C interfacebuilt in theLNBP21 is
automatically resetat power-on. As long as the
Vcc stays be-low the UnderVoltage Lockout
threshold (6.7V typ.), the interface will not respond any I2C com-mand and the System Register
(SR)is initialisedtoall zeroes, thus keeping the
power blocks disabled. Once the Vcc rises above
7.3V, the I2C interface becomes operative and the canbe configuredby the main μP. Thisis due About 500mVof hysteresis providedin the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.
DiSEqCTM IMPLEMENTATION
The LNBP21 helps the system designer to
implement the bi-directional (2.x) DiSEqC protocol al-lowing an easy PWK modulation/
demodulationof the 22KHz carrier. The PWK data
are exchanged between the LNBP21 and the
main μP using logic levels that are compatible with
both 3.3 and 5V mi-crocontrollers. This data
exchangeis made through two dedicated pins,
DSQIN and DSQOUT,in or-derto maintain the
timing relationships between the PWK data and
the PWK modulation as accurate as possible.
These two pins should be directly connectedto
two I/O pinsof the μP, thus leavingto the resident
firmware the taskof encoding and decoding the
PWK datain accordanceto the DiSEqC pro-tocol.
Full complianceof the systemto the specification thus not impliedby the bare useof the LNBP21.
The system designer should also take in
consideration the bus hardware requirements,
that include the source impedanceof the Master
Transmitter measured at 22KHz. To limit the
attenuationat car-rier frequency, this impedance
hastobe 15ohmat 22KHz, droppingto zero ohm DC to allow the power flow towards the
peripherals. This can be simply accomplishedby
the LR termination put on the OUT pinof the
LNBP,as shownin the Typical Application Circuit page5.
Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin canbe directly connectedto the LNB
supply portof the Tuner. Thereis alsono needof
Tone Decoding, thus,itis recommended to
connect the DETIN and DSQOUT pinsto ground avoid EMI.
ADDRESS PIN
Connecting this pinto GND the Chip I2C interface
addressis 0001000, but,itis possibleto choice
among4 different addresses simply setting this
pinat4 fixed voltage levels (see table on page
10).
ELECTRICAL CHARACTERISTICS FOR LNBP SERIES(TJ=0to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,
PCL=0, DSQIN=0, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section
forI2C accessto the system register)
LNBP219/20
LNBP2110/20
GATE AND SENSE ELECTRICAL CHARACTERISTICS(TJ=0to 85°C,VIN =12V)
2C ELECTRICAL CHARACTERISTICS (TJ =0to 85°C, VIN=12V)
ADDRESS PIN CHARACTERISTICS (TJ=0to 85°C, VIN=12V)
TEST CIRCUIT
