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LNBH24-LNBH24PPR-LNBH24TPPR
Dual LNB supply and control IC with step-up and I2C interface
LNBH24Dual LNB supply and control IC with step-up and I²C interface
Features Complete interface between LNBS and I²C bus Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93%@0.5 A) Selectable output current limit through external
resistor Compliant with main satellite receivers output
voltage specification New accurate built-in 22 kHz tone generator
meets widely accepted standards (patent
pending) Fast oscillator start-up facilitates DiSEqC™
encoding Built-in 22 kHz tone detector supports bi-
directional DiSEqC™ 2.0 Very low-drop post regulator and high
efficiency step-up PWM with integrated power
N-MOS allow low power losses Two output pins suitable for bypassing the
output R-L filter and avoiding tone distortion (R-
L filter as per DiSEqC™ 2.0 specs, see typ.
application circuits) Overload and over-temperature internal
protections with I²C diagnostic bits Output voltage and output current level
diagnostic feedback by I²C bits LNB short circuit dynamic protection +/- 4 kV ESD tolerant on output power pins
DescriptionIntended for analog and digital dual satellite
receivers/sat-TV , sat-PC cards, the LNBH24 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-36 ePad, specifically
designed to provide the 13/18 V power supply and
the 22 kHz tone signalling for two independent
LNB down-converters in the antenna dishes
and/or multi-switch box. In this application field, it
offers a dual tuner STBs with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
Table 1. Device summary
Contents LNBH24
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 DiSEqC™ data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 DiSEqC™ 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4 DiSEqC™ 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Data encoding through external tone generator (EXTM) . . . . . . . . . . . . . . 6
2.6 I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.9 Output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10 22 kHz tone diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.11 Minimum output current diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.13 Over-current and short-circuit protection and diagnostic . . . . . . . . . . . . . . 8
2.14 Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2 Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH24 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNBH24 Contents7.2 System register (SR, 1 Byte for each section A and B) . . . . . . . . . . . . . . 16
7.3 Transmitted data (I²C bus write mode) for each section A/B . . . . . . . . . . 16
7.4 Diagnostic received data (I²C read mode) for both sections A/B . . . . . . . 17
7.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7 DiSEqC™ implementation for each section A/B . . . . . . . . . . . . . . . . . . . 18
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Block diagram LNBH24
1 Block diagram
Figure 1. Block diagram
LNBH24 Introduction
2 Introduction
The LNBH24 includes two completely independent sections. Except for the VCC and I²C
inputs, each circuit can be separately controlled and have independent external
components. The specification that follow should be considered equally for both sections
(A/B).
2.1 Application information
This IC has a built-in DC-DC step-up converter which, from a single 8 V to 15 V source,
generates the voltages (VUP) that allow the linear post-regulator to work at a minimum
dissipated power of 0.375 W T yp. @ 500 mA load (the linear post-regulator drop voltage is
internally held at VUP-VOUT=0.75 V typ.). An under voltage lockout circuit will disable the
entire circuit when the supplied VCC drops below a fixed threshold (6.7 V typically).
Note: In this document the VOUT is intended as the voltage present at the linear post-regulator
output (VoRX pin).
2.2 DiSEqC™ data encoding and decoding
The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance
with the standards, and can be selected through I²C interface TTX bit (or TTX pin) and
activated by a dedicated pin (DSQIN) which allows immediate DiSEqC™ data encoding, or
through TEN I²C bit in case the 22 kHz presence is requested in continuous mode. In
standby condition (EN bit LOW). The TTX function must be disabled setting TTX to LOW.
2.3 DiSEqC™ 2.0 implementation
The built-in 22 kHz Tone detector completes the fully bi-directional DiSEqC™ 2.0 (see
Note:) interfacing. Its input pin (DETIN) must be AC coupled to the DiSEqC™ bus, and
extracted PWK data are available on the DSQOUT pin. To comply with the bi-directional
DiSEqC™ 2.0 bus hardware requirements an output R-L filter is needed. The LNBH24 is
provided with two output pins for each section, one for the DC voltage output (VoRX) and one
for the 22 kHz tone transmission (VoTX). The VoTX must be activated only during the tone
transmission while the VoRX provides the 13/18 V output voltage. This allows the 22 kHz
Tone to pass without any losses due to the R-L filter impedance (see Figure 4). During the
22 kHz transmission, in DiSEqC™ 2.0 applications, activated by DSQIN pin or by the TEN
bit, the VoTX pin must be preventively set ON by the TTX function. This can be controlled
both through the TTX pin and the I²C bit. As soon as the tone transmission is expired, the
VoTX must be disabled by setting the TTX to LOW to set the device in the 22 kHz receiving
mode. The 13/18 V power supply is always provided to the LNB from the VoRX pin through
the R-L filter.
2.4 DiSEqC™ 1.X implementation
When the LNBH24 is used in DiSEqC™ 1.x applications the R-L filter is always needed for
the proper operation of the 22 kHz tone generator (patent pending. See Figure 4). Also in
this case, the TTX function must be preventively enabled before to start the 22 kHz data
transmission and disabled as soon as the data transmission has been expired. The tone can
Introduction LNBH24
be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal circuit activates
the 22 kHz tone on the VoTX output with 0.5 cycle ± 25 µs delay from the TTL signal
presence on the DSQIN pin, and it stops with 1 cycle ± 25 µs delay after the TTL signal is
expired.
2.5 Data encoding through external tone generator (EXTM)
In order to improve design flexibility an external tone input pin is available (EXTM). The
EXTM is a Logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using
the LNBH24 integrated tone generator (similar to the DSQIN pin function). In fact, the output
tone waveform characteristics will always be internally controlled by the LNBH24 tone
generator and the EXTM signal will be used as a timing control for DiSEqC tone data
encoding on the VoTX output. A TTL-compatible 22 kHz signal is required for the proper
control of the EXTM pin function. Before sending the TTL signal on the EXTM pin, the VoTX
tone generator must be previously enabled through the TTX function (TTX pin or TTX bit set
HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal code, it activates
the 22 kHz tone on the VoTX output with 1.5 cycles ± 25 µs delay from the TTL signal
presence on the EXTM pin, and it stops with 2 cycles ± 25 µs delay after the TTL signal is
expired (see Figure2).
2.6 I²C interface
The main functions of the IC are controlled via I²C BUS by writing 8 bits on the system
register (SR 8 bits in write mode). On the same register there are 8 bits that can be read
back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the
diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF , OLF),
while three will report the last output voltage register status (EN, VSEL, LLC) received by
the IC (see the diagnostic functions section). Each section (A/B) has two selectable I²C
addresses selectable, respectively, through the ADDR-A and ADDR-B pins (see address
pins characteristics Table 10).
2.7 Output voltage selection
When the IC sections are in standby mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH24 is provided with the LLC I²C bit which increase the selected
voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.
Figure 2. EXTM timings
LNBH24 Introduction
The LNBH24 is also compliant with the USA LNB power supply standards. In order to allow
fast transition of the output voltage from 18 V to 13 V and vice-versa, the LNBH24 is
provided with the VCTRL TTL pin which keeps the output at 13 V when it is set LOW and at
18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH
before using the VCTRL pin to switch the output voltage level. If VCTRL = 1 or floating, then
VOUT = 18.5 V (or 19.5 V if LLC=1). With VCTRL=0 VOUT=13.4 V (LLC= either 0 or 1).
Should be noted that the VCTRL pin controls only the linear regulator VOUT stage while the
step-up VUP voltage is controlled only through the VSEL and LLC I²C bits. That is, even if
VCTRL = 0 (keeping VOUT = 13.4 V) you will have VUP = 19.25 V typ when VSEL = 1 and
20.25 V with VSEL = LLC = 1. This means that VCTRL = 0 must be used only for short
period to avoid the higher power dissipation. In standby condition (EN bit LOW) all the I²C
bits and the TTX pin must be set LOW (if the TTX pin is not used it can be left floating but
the TTX bit must be set LOW during the standby condition).
2.8 Diagnostic and protection functions
The LNBH24 has 5 diagnostic internal functions provided via I²C BUS by reading 5 bits on
the system register (SR bits in read mode). All the diagnostic bits are, in normal operation
(no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature
and over-load protection status (OTF and OLF), while the remaining 3 bits are dedicated to
the output voltage level (VMON), 22 kHz Tone (TMON) and to the Minimum Load Current
diagnostic function (IMON).
2.9 Output voltage diagnostic
When VSEL = 0 or 1 and LLC = 0, the output voltage pin (VoRX) is internally monitored and,
as long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to
"1". The output voltage diagnostic is valid only with LLC = 0 and AUX = 0. Any VMON
information with LLC = 1 and/or AUX = 1 must be disregarded by the MCU.
2.10 22 kHz tone diagnostic
The 22 kHz tone can be internally detected and monitored If the DETIN pin is connected to
the LNB output bus (see typical application circuits) through a decoupling capacitor. The
Tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude
and/or the Tone frequency is out of the guaranteed limits (see TMON limits in the electrical
characteristics in Table 13), the TMON I²C Bit is set to "1".
2.11 Minimum output current diagnostic
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH24 is provided with a minimum output current flag by the
IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA
typically with ITEST=1, and 6 mA with ITEST=0. The minimum current diagnostic function
(IMON) is always active. In order for it to function even in a multi-IRD configuration (multi-
switch), where the supply current could be sunk only from the higher supply voltage
connected to the multi-switch box, the LNBH24 is provided with the AUX I²C bit. To force the
LNBH24 output voltage as the highest voltage on the bus (22 V typ.) during the minimum
current diagnostic phase, the AUX I²C bit can be set HIGH before reading the IMON I²C bit
status. When the AUX bit is set to HIGH, the VOUT is set to 22 V (typ.) and the VUP is set to
Introduction LNBH24
22.75 V (VUP = VOUT + 0.75 V typ.) independent of the VSEL/LLC bits status. If the AUX
function is used to force the VOUT to 22 V, it is recommended to set the AUX bit to LOW as
soon as the minimum current test phase is expired, so that the VOUT voltage will be
controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the
IMON function must be used only with the 22 kHz tone transmission deactivated (TEN = 0
and DSQIN = LOW), otherwise the IMON bit could be set to 0 even if the output current is
below the minimum current thresholds (6 mA or 12 mA).
2.12 Output current limit selection
The linear regulator current limit threshold can be set through an external resistor connected
to ISEL pin. The resistor value defines the output current limit by the equation:
IMAX(A) = 10000/RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable
current limit threshold is 1.0 A typ with RSEL=10 kΩ. The above equation defines the typical
threshold value for each output. However, it is suggested not to exceed for an extended
period a total of current of 1 A from both sections (IOUT_A + IOUT_B < 1 A) in order to avoid
triggering the over-temperature protection.
2.13 Over-current and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the short-
circuit current protection either statically (simple current clamp) or dynamically through the
PCL bit of the I²C SR. When the PCL (pulsed current limiting) bit is set to LOW, the over-
current protection circuit works dynamically: as soon as an overload is detected, the output
is shut down for a time TOFF , typically 900 ms. Simultaneously the diagnostic OLF I²C bit of
the system register is set to "1". After this time has elapsed, the output is resumed for a time
TON = (1/10) TOFF = 90 ms (typ.). At the end of TON, if the overload is still detected, the
protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no
overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to
LOW. Typical TON+TOFF time is 990 ms and an internal timer determines it. This dynamic
operation can greatly reduce the power dissipation in short-circuit condition, still ensuring
excellent power-on start-up in most conditions. However, there could be some cases in
which a highly capacitive load on the output may cause a difficult start-up when the dynamic
protection is chosen. This can be solved by initiating any power start-up in static mode
(PCL=1) and then switching to the dynamic mode (PCL = 0) after a chosen amount of time
depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to
"1" when the current clamp limit is reached and returns LOW when the overload condition is
cleared.
2.14 Thermal protection and diagnostic
The LNBH24 is also protected against overheating. When the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulator are shut off, and the diagnostic
OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when
the junction is cooled down to 135 °C (typ.).
Note: External components are needed to comply to bi-directional DiSEqC™ bus hardware
requirements. Full compliance of the whole application with DiSEqC™ specifications is not
implied by the use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.
LNBH24 Pin configuration Pin configuration
Figure 3. Pin connections
Table 2. Pin description
Pin configuration LNBH24
Table 2. Pin description (continued)
LNBH24 Maximum ratings
4 Maximum ratings
Note: Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.
Note: 1 The BYP pin is intended only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent damage to the device.
Table 3. Absolute maximum ratings
Table 4. Thermal data
Application circuit LNBH24
5 Application circuit
Figure 4. Typical application circuit
LNBH24 Application circuit
Table 5. Bill of material (valid for A and B sections except for C1, C2, C7, C8 and R1)
I²C bus interface LNBH24 I²C bus interface
Data transmission from main MCU to the LNBH24 and vice-versa takes place through the 2
wires I²C bus Interface, consisting of the 2 SDA and SCL lines (pull-up resistors to positive
supply voltage must be externally connected).
6.1 Data validity
As shown in Figure 5 the data on the SDA line must be stable during the high semi-period of
the clock. The HIGH and LOW state of the data line can only change when the clock signal
on the SCL line is LOW.
6.2 Start and stop condition
As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3 Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4 Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (LNBH24) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH24 will not generate acknowledge if the
VCC supply is below the under-voltage lockout threshold (6.7 V typ.).
6.5 Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH24, the MCU can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and sends
the new data. This approach of course is less protected from malfunctions and decreases
the noise immunity.
LNBH24 I²C bus interface
Figure 5. Data validity on the I²C bus
Figure 6. Timing diagram of I²C bus
Figure 7. Acknowledge on the I²C bus
