LNBH221PD ,DUAL LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEPIN CONFIGURATIONSPIN NUMBERSECT:SYMBOL NAME FUNCTIONABV Supply Input 8V to 15V supply. A 220µF byp ..
LNBH221PD ,DUAL LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Input Voltage-0.3 to 16 VCCV DC Input Volta ..
LNBH221PD-TR ,DUAL LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACEBLOCK DIAGRAM
LNBH221PD-LNBH221PD-TR
DUAL LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
1/18April 2004 ALL THE FEATURES ARE THE SAME FOR
BOTH SECTION COMPLETE AND INDEPENDENT
INTERFACE BETWEEN LNBs AND
RELEVANTI2CTM BUS BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION AND
HIGH EFFICIENCY (Typ. 93%@ 500mA) LNB OUTPUT CURRENT GUARANTEED UP 500mA BOTH COMPLIANT WITH EUTELSAT AND
DIRECTV OUTPUT VOLTAGE
SPECIFICATION ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR SUITS WIDELY ACCEPTED
STANDARDS FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM 2.0 SEMI-LOWDROP POST REGULATOR AND
HIGH EFFICIENCY STEP-UP PWM FOR
LOW POWER LOSS: Typ. 0.56W@ 125mA TWO OUTPUT PINS SUITABLE TO BYPASS
THE OUTPUT R-L FILTER AND AVOID ANY
TONE DISTORSION (R-L FILTER AS PER
DiSEqC 2.0 SPECs, see application circuiton
pag.4) OVERLOAD AND OVER-TEMPERATURE
INTERNAL PROTECTIONS OVERLOAD AND OVER-TEMPERATUREI2C
DIAGNOSTIC BITs LNB SHORT CIRCUIT SOA PROTECTION
WITHI2C DIAGNOSTIC BIT +/- 4KV ESD TOLERANT ON INPUT/
OUTPUT POWER PINS
DESCRIPTIONIntended for analog and digital DUAL Satellite
STB receivers/SatTV, sets/PC cards, the
LNBH221isa voltage regulator and interface IC,
assembled in POWER SO-36, specifically
designedto provide the power 13/18V, and the
22KHz tone signalling for two independent LNB
down convertersortoa multiswitch box that could independently powered and set.In this applica-
tion field,it offersa complete solution with ex-
tremely low component count, low power dissipa-
tion together with simple design andI2CTM stan-
dard interfacing.
LNBH221DUAL LNB SUPPLY AND CONTROL IC
WITH STEP-UP CONVERTER ANDI2C INTERFACE
PRELIMINARY DATA
BLOCK DIAGRAM
LNBH2212/18
ABSOLUTE MAXIMUM RATINGSAbsoluteMaximum Ratingsare those values beyond which damagetothe device may occur. Functional operation under theseconditionis
not implied.
THERMAL DATA
PIN CONFIGURATION (top view)
LNBH2213/18
TABLEA: PIN CONFIGURATIONS
LNBH2214/18
TYPICAL APPLICATION CIRCUITS FOR EACH SECTION:A andB
APPLICATION CIRCUIT FOR DiSEqC 1.x AND OUTPUT CURRENT UP TO 500mA
APPLICATION CIRCUIT FOR Bi-directional DiSEqC 2.0 AND OUTPUT CURRENT UP TO 500mAC8,D3andD4are neededto protectthe output pins fromany negative voltage spikes during high speed voltage transitions.
(*): R-L filtertobe used accordingto EUTELSAT recommendationto implementthe DiSEqCTM 2.0, (see DiSEqCTM implementationon
page8).If bidirectional DiSEqCTM2.0isnot implementeditcanbe removed both withC8 andD4.
(**)Donot leave these pins floatingifnot used.
(***)Tobe solderedas closeas possibleto relative pins.
LNBH2215/18
APPLICATION INFORMATIONBasically, the LNBH221 includes two circuits that are completely independent. Each circuit can be
separately controlled and must haveits independent external components. All the below specification
mustbe considered equalfor each section.
ThisIC hasa builtin DC/DC step-up controller that, froma single supply source ranging from8to 15V,
generates the voltages(VUP) thatlet the linear post-regulatorto workata minimum dissipated powerof typ.@ 500mA load (the linear regulator drop voltageis internally kept at:VUP-V OUT =2V typ.). An
UnderVoltage Lockout circuit will disable the whole circuit when the supplied VCC drops belowa fixed
threshold (6.7V typically). The internal 22KHz tone generatoris factory trimmedin accordanceto the
standards, and canbe controlled eitherby theI2CTM interfaceorbya dedicated pin (DSQIN) that allows
immediate DiSEqCTM data encoding (*). When the TEN (Tone ENable)I2C bititis setto HIGH,a
continuous 22KHz toneis generatedon the output regardlessof the DSQIN pin logic status.
The TEN bit must be set LOW when the DSQIN pinis used for DiSEqCTM encoding. The fully
bi-directional DiSEqCTM 2.0 interfacingis completed by the built-in 22KHz tone detector. Its input pin
(DETIN) must be AC coupledto the DiSEqCTM bus, and the extracted PWK data are available on the
DSQOUT pin (*).To complyto the bi-directional DiSEqCTM 2.0 bus hardware requirementsan output R-L
filteris needed. The LNBH221is provided with two output pins: theVOTXto be used during the tone
transmission and theVORXtobe used when the toneis received. This allows the 22KHz Toneto pass
without any losses dueto the R-L filter impedance (see DiSeqC 2.0 application circuit on page 5).In
DiSeqC 2.0 applications during the 22KHz transmission activatedby DSQIN pin (or TENI2 Cbit), theOTX pin must be preventively set ONby the TTXI2Cbit and, both the 13/18V power supply and the
22KHz tone, are providedby meanofVOTX output. As soon as the tone transmissionis expired, the
VOTX must be setto OFFby setting the TTXI2Cbitto zero and the 13/18V power supplyis providedto
the LNBby the VORX pin through the R-L filter. When the LNBH221is usedin DiSeqC 1.x applications the
R-L filteris not required (see DiSeqC 1.x application circuiton pag.5), the TTXI2Cbit mustbe kept always HIGHso that, theVOTX output pin can provide both the 13/18V power supply and the 22KHz tone,
enabledby DSQIN pinorby TENI2C bit.All the functionsof thisIC are controlled viaI2CTM busby writing bitson the System Register (SR,8 bits). The same register canbe read back, and two bits will report the
diagnostic status. When theICis putin Stand-by (ENbit LOW), the power blocks are disabled.
When the regulator blocks are active (ENbit HIGH), the output canbe logic controlledtobe13or18Vby
meanof the VSEL bit (Voltage SELect) for remote controllingof non-DiSEqC LNBs. Additionally, the
LNBH221is provided with the LLCI2Cbit that increase the selected voltage value (+1V when VSEL=0
and +1.5V when VSEL=1)to compensate for the excess voltage drop along the coaxial cable (LLCbit
HIGH). By meanof the LLC bit, the LNBH221is also compliantto the American LNB power supply
standards that require the higher output voltage levelto 19.5V (typ.) (insteadof 18V),by simply setting the
LLC=1 when VSEL=1.In orderto improve design flexibility andto allow implementationof newcoming
LNB remote control standards,an analogic modulation input pinis available (EXTM). appropriate DC blocking capacitor mustbe usedto couple the modulating signal sourceto the EXTM
pin. Alsoin this case, theVOTX output mustbe set ON during the tone transmissionby setting the TTXbit
high. When external modulationis not used, the relevant pin canbe left open. The current limitation block SOA type:if the output portis shortedto ground, the SOA current limitation block limits the short circuit
current(ISC)at typically 300mAor 200mA respectively forV OUT 13Vor 18V,to reduce the power
dissipation. Moreover,itis possibleto set the Short Circuit Current protection either statically (simple
current clamp)or dynamicallyby the PCLbitof theI2C SR; when the PCL (Pulsed Current Limiting)bitis
setto LOW, the overcurrent protection circuit works dynamically,as soonasan overloadis detected, the
outputis shut-down fora time TOFF, typically 900ms. Simultaneously the OLFbitof the System Register setto HIGH. After this time has elapsed, the outputis resumed fora timeTON =1/10T OFF (typ.).Atthe
endof TON,if the overloadis still detected, the protection circuit will cycle again through TOFF and TON.At
the endofa full TONin which no overloadis detected, normal operationis resumed and the OLFbitis
resetto LOW.TypicalTON+T OFF timeis 990ms anditis determinedby an internal timer. This dynamic
operation can greatly reduce the power dissipationin short circuit condition, still ensuring excellent
power-on startupin most conditions. However, there couldbe some casesin whichan highly capacitive
load on the output may causea difficult start-up when the dynamic protectionis chosen. This can be
solved by initiating any power start-upin static mode (PCL=HIGH) and then switchingto the dynamic
mode (PCL=LOW) aftera chosen amountof time. Whenin static mode, the OLFbit goes HIGH when the
current clamp limitis reached and returns LOW when the overload conditionis cleared. ThisICis also
LNBH2216/18
protected against overheating: when the junction temperature exceeds 150°C (typ.), the step-up
converter and the linear regulator are shut off, and the OTF SRbitis setto HIGH. Normal operationis
resumed and the OTFbitis resetto LOW when the junctionis cooled downto 140°C (typ.).
(*): External componentsare neededto complyto bi-directional DiSEqCTM bus hardware requirements. Full complianceofthe whole
applicationto DiSEqCTM specificationsisnot impliedbytheuseofthisIC.
NOTICE: DiSEqCisa trademarkof EUTELSAT.I2Cisa trademarkof Philips Semiconductors.
2C BUS INTERFACE (one for each section)
Data transmission from mainµPto the LNBH221 and viceversa takes place through the2 wiresI2C bus
interface, consistingof the two lines SDA and SCL (pull-up resistorsto positive supply voltage mustbe
externally connected).
DATA VALIDITY shownin fig.1, the dataon the SDA line mustbe stable during the high periodof the clock. The HIGH
and LOW stateof the data line can only change when the clock signalon the SCL lineis LOW.
START AND STOP CONDITIONS shownin fig.2a start conditionisa HIGHto LOW transitionof the SDA line while SCLis HIGH.
The stop conditionisa LOWto HIGH transitionof the SDA line while SCLis HIGH.A STOP conditions
mustbe sent before each START condition.
BYTE FORMATEvery byte transferredto the SDA line must contain8 bits. Each byte mustbe followedbyan
acknowledge bit. The MSBis transferred first.
ACKNOWLEDGEThe master (µP) putsa resistive HIGH levelon the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (LNBH221) that acknowledges hasto pull-down (LOW) the SDA line during the
acknowledge clock pulse,so that the SDA lineis stable LOW during this clock pulse. The peripheral which
has been addressed hasto generatean acknowledge after the receptionof each byte, otherwise the SDA
line remainsat the HIGH level during the ninth clock pulse time.In this case the master transmitter can
generate the STOP informationin order to abort the transfer. The LNBH221 won't generate the
acknowledgeif the VCC supplyis below the Undervoltage Lockout threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGEMENTAvoidingto detect the acknowledgeof the LNBH221, theµP can usea simpler transmission: simplyit
waits one clock without checking the slave acknowledging, and sends the new data.
This approachof courseis less protected from misworking and decreases the noise immunity.
Figure1: DATA VALIDITY ON THEI2 CBUS
LNBH2217/18
Figure2: TIMING DIAGRAM ONI2 CBUS
Figure3: ACKNOWLEDGE ONI2 CBUS
LNBH221 SOFTWARE DESCRIPTION (same for both section)INTERFACE PROTOCOL
The interface protocol comprises:A start condition (S)A chip address byte= hex10/11 (the LSBbit determines read(=1)/write(=0) transmission)A sequenceof data(1 byte+ acknowledge)A stop condition (P)
ACK= Acknowledge Start Stop
R/W= Read/Write
SYSTEM REGISTER (SR,1 BYTE)R,W= read and writebit Read-onlybit
Allbits resetto0at Power-On
LNBH2218/18
TRANSMITTED DATA(I2C BUS WRITE MODE)When the R/Wbitin the chip addressis setto0, the mainµP can writeon the System Register (SR)of the
LNBH221 viaI2C bus. Only6 bits outof the8 available canbe writtenby theµP, since the remaining2 are
leftto the diagnostic flags, and are read-only. don't care.
Valuesare typical unless otherwise specified
RECEIVED DATA(I2C bus READ MODE)The LNBH221 can provideto the Mastera copyof the SYSTEM REGISTER information viaI2 Cbusin
read mode. The read modeis Master activatedby sending the chip address with R/Wbit setto1. the following master generated clocks bits, the LNBH221 issuesa byteon the SDA data bus line (MSB
transmitted first). the ninth clockbit the MCU master can: acknowledge the reception, startingin this way the transmissionof another byte from the LNBH221;no acknowledge, stopping the read mode communication.
While the whole registeris read back by theµP, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBH221.
Values are typical unless otherwise specified
POWER-ONI2C INTERFACE RESETTheI2C interface builtin the LNBH221is automatically resetat power-on.As longas the VCC stays below
the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respondto anyI2C command and
the System Register (SR)is initializedtoall zeroes, thus keeping the power blocks disabled. Once the
VCC rises above 7.3V typ, theI2C interface becomes operative and the SR canbe configuredby the main
µP. Thisis dueto 500mVof hysteresis providedin the UVL thresholdto avoid false retriggeringof the
Power-On reset circuit.
ADDRESS PinConnecting this pinto GND the ChipI2C interface addressis 0001000, but,itis possibleto choice among different addresses simply setting this pinat4 fixed voltage levels (see tableon page 10).
LNBH2219/18
DiSEqCTM IMPLEMENTATIONThe LNBH221 helps the system designerto implement the bi-directional DiSEqC 2.0 protocolby allowing easy PWK modulation/demodulationof the 22KHz carrier. The PWK data are exchanged between the
LNBH221 and the mainµP using logic levels that are compatible with both 3.3 and 5V microcontrollers.
This data exchangeis made through two dedicated pins, DSQIN and DSQOUT,in orderto maintain the
timing relationships between the PWK data and the PWK modulationas accurateas possible. These two
pins shouldbe directly connectedto two I/O pinsof theµP, thus leavingto the resident firmware the task encoding and decoding the PWK datain accordanceto the DiSEqC protocol. Full complianceof the
systemto the specificationis thus not impliedby the bare useof the LNBH221. The system designer
should also takein consideration the bus hardware requirements; that canbe simply accomplishedby the
R-L termination connectedon the VOUT pinsof the LNBH221,as shownin the Typical Application Circuit page4.To avoid any losses dueto the R-L impedance during the tone transmission, the LNBH221 has
dedicated output(VO TX) that,ina DiSEqC 2.0 application,is connected after the filter and must be
enabledby setting the TTX SRbit HIGH only during the tone transmission (see DiSEqC 2.O operation
descriptionon page5).
Unidirectional (1.x) DiSEqC and non-DiSEqC systems normally don't need this termination, and theVOTX
pin canbe directly connectedto the LNB supply portof the Tuner (see DiSeqC 1.x application circuiton
pag.4). Thereis alsono needof Tone Decoding, thus DETIN and DSQOUT pins canbe left unconnected
and the Toneis providedby the VOTX.
ELECTRICAL CHARACTERISTICS OF EACH SECTION(A andB)=0to 85°C, EN=1, TTX=0/1, LLC=VSEL=TEN=PCL=0, DSQIN=LOW, VIN=12V, IOUT=50mA, unless
otherwise specified. See software description sectionforI2C accessto the system register)
