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LMK04033BISQX/NOPB
Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com SNOSAZ8J –SEPTEMBER 2008–REVISED SEPTEMBER 2011
LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Checkfor Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033
1FEATURES
23• Cascaded PLLatinum™ PLL Architecture • Support Clock Rates upto 1080 MHz PLL1 • Default Clock Output (CLKout2)at power up Phase Detector Rateof upto40 MHz • Five Dedicated Channel Divider and Delay
Blocks– Integrated Low-Noise Crystal Oscillator
Circuit • Pin Compatible Familyof Clocking Devices Dual Redundant Input Reference Clock • Industrial Temperature Range: -40to85°C
with LOS • 3.15Vto 3.45V Operation PLL2 • Package: 48 Pin WQFN (7.0x 7.0x 0.8 mm) Normalized[1 Hz] PLL Noise Floorof-
224 dBc/Hz APPLICATIONS Phase Detector Rate upto 100 MHz • Data Converter Clocking Input Frequency-Doubler • Wireless Infrastructure Integrated Low-Noise VCO • Networking, SONET/SDH, DSLAM Ultra-Low RMS Jitter Performance • Medical 150fs RMS Jitter (12 kHz– 20 MHz) • Military/ Aerospace 200fs RMS Jitter (100 Hz– 20 MHz) • Test and Measurement LVPECL/2VPECL, LVDS, and LVCMOS outputs • Video
DESCRIPTIONThe LMK04000 familyof precision clock conditioners provides low-noise jitter cleaning, clock multiplication and
distribution without the need for high-performance voltage controlled crystal oscillators (VCXO) module. Usinga
cascaded PLLatinum™ architecture combined with an external crystal and varactor diode, the LMK04000 family
provides sub-200 femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consistsof two high-performance phase-locked loops (PLL),a low-noise crystal
oscillator circuit, anda high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) providesa low-
noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 canbe configured VCXO moduleor use the integrated crystal oscillator withan external crystal and useda very narrow loop bandwidth, PLL1 uses the superior close-in phase noise the moduleor the crystalto clean the input clock. The outputof PLL1is usedas whereit locks the integrated VCO. The loop bandwidthof PLL2 can be far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the inputs, five differential outputs, with lossof signal detection and automaticof the consistsofa programmable divider,a phase synchronizationaor LVCMOS output buffer. The default clock availableon an initial clock for the field-programmable gate (FPGA) or cleaner during the system powerup sequence.
