LMH1983SQ/NOPB ,3G/HD/SD Video Clock Generator with Audio Clock 40-WQFN -40 to 85 SNLS309I–APRIL 2010–REVISED DECEMBER 20145 Description (continued)When locked to reference, an int ..
LMH6321MR ,300 mA High Speed Buffer with Adjustable Current Limit 8-SO PowerPAD -40 to 125ELECTRICAL CHARACTERISTICSThe following specifications apply for Supply Voltage = ±15V, V = 0, R≥ 1 ..
LMH6502MA ,Wideband, Low Power, Linear-in-dB Variable Gain AmplifierApplicationstion, the unused input can easily be tied to ground (or to an Variable attenuatorvirtua ..
LMH6502MAX ,Wideband, Low Power, Linear-in-dB Variable Gain AmplifierFeatures™ = ±5V, T = 25˚C, R =1kΩ,R = 174Ω,R = 100Ω,AThe LMH 6502 is a wideband DC coupled differen ..
LMH6503MA ,Wideband, Low Power, Linear Variable Gain AmplifierApplicationstion, the unused input can easily be tied to ground (or to an Variable attenuatorvirtua ..
LMH6503MA ,Wideband, Low Power, Linear Variable Gain AmplifierFeatures™ ±The LMH 6503 is a wideband DC coupled differential input V = 5V, T = 25˚C, R =1kΩ,R = 17 ..
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LMH1983SQ/NOPB
3G/HD/SD Video Clock Generator with Audio Clock
LOOP
FILTER
27 MHz
VCXO
LMH1983
FPGA
A/V Frame Sync with
Downconverter, 1080p/59.94 SDI out
H sync
V sync
27 MHz (PLL1)
24.576 MHz (PLL4)
525i/29.97 SDI out
+ embedded audio
CLKout1
Hin
29.97 Hz (TOF1)
59.94 Hz (TOF3)
Product
Folder
Sample &
Buy
LMH1983 3G/HD/SD Video Features 3 DescriptionThe LMH1983isa highly-integrated programmable Four PLLsfor Simultaneous A/V Clock Generation audio/video (A/V) clock generator intended for– PLL1:27or 13.5 MHz broadcast and professional applications. It can PLL2: 148.5or 74.25 MHz replace multiple PLLs and VCXOs used in
applications supporting SMPTE serial digital video– PLL3: 148.5/1.001or 74.25/1.001 MHz (SDI) and digital audio AES3/EBU standards.It offers– PLL4: 98.304 MHz/2X(X=0to 15) low-jitter reference clocks for any SDI transmitterto• 3x2 Video Clock Crosspoint meet stringent output jitter specifications without
additional clock cleaning circuits.• Flexible PLL Bandwidthto Optimize Jitter
Performance and Lock Time The LMH1983 features automatic input format Soft Resynchronizationto New Reference detection, simple programmingof multiple A/V output
formats, genlock or digital free-run modes, and• Digital Holdoveror Free-runon Lossof Reference override programmability of various automatic• Status Flags for Lossof Reference and Lossof functions. The recognized input formats include HVFPLL Lock syncs for the major video standards, 27 MHz, 10 3.3V Single Supply Operation MHz, and 32/44.1/48/96 kHz audio word clocks.I2C Interface with Address Select Pin(3 States) The dual-stage PLL architecture integrates four PLLs
with three on-chip VCOs. The first stage (PLL1) uses
2 Applications an external low-noise 27 MHz VCXO with narrow
loop bandwidthto providea clean reference clock for• Triple Rate (3G/HD/SD) SDI SerDes the next stage. The second stage (PLL2, 3, 4)• FPGA Reference Clock Generation/Cleaning consistsof three parallel VCO PLLs for simultaneous Audio Embedor De-embed generationof the major digital A/V clock fundamental
rates, including 148.5 MHz, 148.5/1.001 MHz, and• Video Cameras 98.304 MHz (4× 24.576 MHz). Each PLL can• Frame Synchronizers (Genlock, DARS) generatea clock anda timing pulseto indicate topof• A-Dor D-A Conversion, Editing, Processing Cards frame (TOF). Keyers and Logo Inserters
Device Information(1)• Formator Standards Converters• Video Displays and Projectors• A/V Test and Measurement Equipment
(1) Forall available packages, see the orderable addendumat
the endofthe datasheet.
Typical Application Block Diagram
