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LMH0340SQX/NOPB
3Gbps, HD, SD, DVB-ASI SDI Serializer and Driver with LVDS Interface
ControlSMPTE Cable Driver
LOCK
RESET
SCK
SDA
SMBus
TXOUT
PLL Clock
GenerationLVDS Receivers
TXCLK
TX0
TX2
TX3
TX4
En
lle
l to
Se
ria
l 5SMB_CS
DVB_ASI
GPIO[2:0]
LMH0040, LMH0050
LMH0070, LMH0340
www.ti.com SNLS271I–APRIL 2007–REVISED APRIL 2013
Gbps, HD, SD, DVB-ASI SDI Serializer and Cable Driver With LVDS Interface
Checkfor Samples: LMH0040, LMH0050, LMH0070, LMH0340
1FEATURES DESCRIPTIONThe LMH0340/0040/0070/0050 SDI Serializers are
LVDS Interfaceto Host FPGA partof TI’s familyof FPGA-Attach SER/DES products
• No External VCOor Clock Ref Required supporting 5-bit LVDS interfaces with FPGAs. An
Integrated Variable Output Cable Driver FPGA Host will format data with suppliedIP such that
the outputof the LMH0340is compliant with the
• 3.3V SMBus Configuration Interface requirementsof DVB-ASI, SMPTE 259M-C, SMPTE
• Integrated TXCLK PLL Cleans Clock Noise 292M and SMPTE 424M standards. See Table1 for
• Small 48-Pin WQFN Package details on which Standards are supported per device.
Industrial Temperature range: -40°Cto 85°C The interface between the SER (Serializer) and the
FPGA consistsofa5 bit wide LVDS data bus, an
APPLICATIONS LVDS clock and an SMBus interface. The
LMH0340/0040/0070 SER devices include an
• SDI Unterfaces for: integrated cable driver whichis fully compliant withall
– Video Cameras of the SMPTE specifications listed above. The
DVRs LMH0050 hasa CML output driver that can drivea
differential transmission lineor interfacetoa cable
– Video Switchers driver.
– Video Editing SystemsThe FPGA-Attach SER/DES familyis supportedbya
suite of IP which allows the design engineer to
KEY SPECIFICATIONSquickly develop video applications using the
• Output Compliant With SMPTE 424M, SMPTE SER/DES products. The SER is packaged ina
292M, SMPTE 259M-C and DVB-ASI (See physically small 48-pin WQFN package.
Table1) Typical Power Dissipation: 440 mW General Block Diagram 30ps Typical Output Jitter (HD, 3G)