LM4312SN/NOPB ,Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin 48-X2QFN -40 to 85Pin DescriptionsNo. Description(1)Pin Name I/O, Typeof Pins RGB SerializerMPL-2 SERIAL BUS PINSDD0P ..
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LP2951C , 100mA Low Dropout Voltage Regulators
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LP2951CD ,100mA, 3.3V or Adjustable, Low Power Low Dropout Voltage Regulator with Error Flag OutputMAXIMUM RATINGS (T = 25°C, unless otherwise noted.)ARating Symbol Value UnitInput Voltage V 30 VdcC ..
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LM4312SN/NOPB
Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin
PRODUCT PREVIEW
LM4310 DeserializerLM4312 SerializerPLL
B[5:0]
R[5:0]
G[5:0]
RGB Display
VGA
PD*
B[7:0]
Three
256 x 8
LUTs
Configuration
DD0
DD1
Config. RDS
Mode24
PCLK
LM4312
www.ti.com SNLS265A –MAY 2008–REVISED MAY 2013
LM4312 Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with
Optional Dithering and Look Up Table
Checkfor Samples: LM4312
1FEATURES DESCRIPTIONThe LM4312isa MPL-2 Serializer (SER) that accepts
RGB Display Interfaceto >640x 480 (VGA) a 24-or 18-RGB interface and serializes this wide
Resolution busto3 differential signals. The optional Dithering
• 24or 18-bit RGB Transport feature can reduce 24-bit RGBto 18-bit RGB. The
24–to–18-bit RGB Dithering Option optional Look Up Table (ThreeX 256X8bit RAM)is
provided for independent color correction. 18-bit
• Look Up Table Option for Independent Color Bufferless displays from QVGA (320x 240) upto
Correction Option >VGA (640x 480) pixels are supported.
• Robust MPL-2 Differential SLVS Interface The interconnect is reduced from 28 LVCMOS
• SPI Interface for Configuration/ Control and signals (RGB888+V+H+DE+PCLK)to only3 active
LUT Options differential signals (DD0P/M, DCP/M, DD1P/M) with
Low Power Consumption& SLEEP State the LM4312 Serializer and companion LM4310
Deserializer easing flex interconnect design, size
• Auto Power Down on STOP PCLK constraints and cost.
• Automatically Generates Frame Sequence Bits
for Resync upon Dataor Clock Error The LM4312 SER residesby the application, graphics baseband processor and translates the wide
• Odd Parity Generation parallel video bus from LVCMOS levels to serial
MPL-2 levels for transmission overa flex cable and
SYSTEM BENEFITS PCB tracesto the DES locatedin the display module.
Dithered Data Reduction Whenin Power_Down, the SERis putto sleep and
• Independent RGB Color Correction draws less than 10μA. The SER can be powered
down by stopping the PCLKor by assertingits PD*
• 24-bit Color Inputinput pin.
• Small Robust InterfaceThe LM4312 implements the physical layerof the
• Low Power& Low EMI MPL-2 Interface and features robust common-mode
noise rejection.
Typical Application Diagram- Bridge Chips- 24-bitto 18-bit RGB
