LM1880J ,NO-HOLDS VERTICAL/HORIZONTALFeatures
The LM1880 uses compatible Linear/ 12L technology to pro-
duce the first T.V. horizont ..
LM1880J ,NO-HOLDS VERTICAL/HORIZONTALBlock Diagram
FILTER
1 NORIZ MI MT
sllrYl1"ilt, ' PHASE GATE
DETECTOR FORMER
M " MI HST
..
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LM1880J
NO-HOLDS VERTICAL/HORIZONTAL
LM1880
National .
[ Semiconductor
LM1880 No-Holds Vertical/Horizontal
General Description
The LM1880 uses compatible Linear/RL technology to pro-
duce the first T.V. horizontal and vertical processing system
which completely eliminates the hold controls. The heart of
the system is a precision 32 times horizontal frequency VCO
which is designed to use a low-cost ceramic resonator as a
tuning element.
The VCO signal is divided down in the horizontal section to
produce a pre-driver output which is locked to negative sync
by means of an on-chip phase detector. The vertical output
ramp is injection-locked by vertical sync subject to a sync
window derived from the vertical countdown section. A gate
pulse centered on the chroma burst is also provided.
Features
I: No frequency set-up required for horizontal or vertical
u Ceramic resonator frequency reference
a Accurate horizontal pre-driver duty cycle
" Vertical sync window referenced to horizontal
u Precise interlaced vertical output
" APC loop parameters completely adjustable
" Vertical retrace time adjustable
" Chroma burst gate output
a Internal voltage regulator
u Improved vertical lock time
Block Diagram
tle -A--,
T , 'ill'
a 32 l" . a
no SHUNT 503.5 kHz Mit '. nomz
REF o---- REG vco comma a.2 00T
J.. 2.
LOOP é - t H
FILTER "
FLYBACK 1 Mttt2 BORST VERTICM. VERTICAL It VERTICAL
snmoom C PHASE GATE mama RAMP OUT
DETECTOR FORMER comma FORMER
In La Inn £1 = in
uomz BURST VERTICAL VERTICAL
svuc GATE svuc MTRACE
OUT TIMING
TL/H/7915-1
Absolute Maximum Ratings
If Mllltary/Aerospace specified devlces are required,
please contact the National Semiconductor Sales
Office/Dlstrlbutors tor avallablllty and speclflcatlons.
Sync. Input Voltage (Pins IO, 14)
Sawtooth Input Voltage (Pin 1)
Package Dissipation, TA = +25°C
5 Vp-p
5 Vp-p
1400 mW
Supply Current (Pin 9) 40 mA Above TA = 25''C, Derate Based on
Output Voltage (Pins 8, 12, 13) 12V TJ(MAX) = + 150°C and eJA = + 90°C/W
Output Current Storage Temperature Range - 55°C to + 150°C
','2, $2 'fl 'Jd Operating Temperature Range 0°C to + 70°C
m m . a
Pin 13 10 m A Lead Temperature (Soldering, 10 sec.) + 260 C
Electrical Characteristics (T est Circuit, all SW normally pos. 1, TA = 25°C, v+ = 12V)
Parameter Condltlons Min Typ Max Units
Regulated Voltage (Pin 9) 8.2 8.7 9.2 V
Supply Current (Pin 9) SW 7 Pos. 2, V9 = + 7.5V 12 18 24 mA
VCO Reference Voltage (Pin 3) 5.1 V
VCO ControlCurrent(Pin 2) V2 = 5V 0.25 1.0 11A
Horizontal Phase Detector SW1, SW 4 Pos. 2, 0 3 0 5 m A
Sink Current(Pin 2) V1 = 3.9V, V2 == 5V . .
Horizontal Phase Detector SW1,SW 4 Pos. 2, 0 3 0 5 m A
Source Current(Pin 2) V1 = 1.9V, V2 = 5V . .
Horizontal Output Leakage Change SW 3 to Pos. 2 1 50 A
(Pin 8, OFF Condition) with Pin a High "
Horizontal Output Saturation Voltage Change SW 3 to Pos. 2 0 15 O 4 V
(Pin 8, ON Condition) with Pin 8 Low . .
Vertical Output Saturation SW 3, SW 5 Pos. 2
Voltage (Pin 12) 0.25 0.5 V
Burst Gate Saturation SW l, SW 4 Pos. 2,
Voltage (Pin 13) VI = 1.9V 0.15 0.4 V
Horizontal Oscillator Free-Running SW 2 Pos. 2
Frequency (Pin to, (Note 1) 15,550 15,750 15,950 Hz
Horizontal Osgllator Maximum V2 = 7V 16,300 Hz
Frequency (Pin 8)
Horizontal Isfetor Minimum V2 = 3V 15,150 Hz
Frequency (Pin 8)
Vertical Minimum Lock Frequency (Pin 12) fH = 15,734 Hz 55.0 Hz
Vertical Maximum Lock Frequency (Pin 12) SW 6 Pos. 2, fH = 15,734 Hz 61.7 Hz
Note 1: Assumes ceramic resonator tn = 503.48 kHz.
Design Parameters (Application Circuit)
Parameter Conditions Mln Typ Max Units
Horizontal Pull-In Range i 600 Hz
Horizontal Static Phase Error (S.P.E.) AfH = d: 600 Hz i0.5 p8
Horizontal Output Duty Cycle 50 %
Horizontal Oscillator Supply Sensitivity - 1 Hz/ V
Vertical Output Retrace Time 600 ps
Burst Gate Width Flyback Width = 12 us 5 us
088”!“
LM1880
Test Circuit
12V 7.5V
Order Number LM1880J
Typical Performance Characteristics
, VCO Control Chttrtttttttrltttltt
CONTROL VOLTAGE PIN 2 (V)
".5 " 15.5 18 15.5
”DRIZONTAL FREQUENCY (MM
TL/H/7915-3
See NS Package Number J14A
Horizontal Free-Running
Fueuumcv DRIFT (Hz)
-25 il " M hi
AMBIENT TEMPERATURE i' C)
TL/H/7915-2
Frequency " Temperature
TL/H/7916-4
Typical Application
'ill BURST
NW <3 GATE our
-d L- JI
FLVBACK M . I 1 FLYBACK HORIZ
so V” I SAWTOOTH SYNC
0.1 HF Cl? tl.IPF
I 2 LOOP BURST >50 COMPOSITE
Ct I l C: FILTER GATE SYNC 20 tttrp
0.01pF tuF Ry
. I . won
3.3k 3 ‘nc VERTICAL " OVERTICAL
REF our RAMP swncn
4 VCO VERT RETRACE av
our TIMING ttik
503.5 kHz
cc:= nssonnon*
VERT J
" svm: I
Cl? 0.05 "
VCO " " v (unreg)
0.001uF
7 HDHIZ 3 T0 HORIZONTAL
Ir"" our -o DRIVER
Printed Circuit Layout
'MuRata Corporation of America, Part No. CSBSOGB
(COMPONENT SIDE)
TL/H/7915-5
TL/H/7ir15-6
0881M”
LM1880
External Components (Application Circuit)
Component
Typical
0.1 p.F
0.05yF
0.1 pF
Comments
Burst Gate series resistor.
Burst Gate shunt resistor, works
with R91 to divide flybaek pulse
and set Burst Gate amplitude.
R91 + R92
Flyback Sawtooth integrator
resistor, works with Ct to
integrate flyback pulse to 1 Vp-p
min sawtooth. Forq = 0.1 pF,
85VFLYBACK
Flyback Sawtooth integrator
capacitor.
Sawtooth input coupling
capacitor.
Horizontal Sync input coupling
resistor.
Rh = 0.4 X VSYNC p-p k0.
Horizontal Sync input coupling
capacitor, blocks vertical sync
components.
Vertical sync input integrator
resistor.
Vertical sync input integrator
capacitor, works with RV to
integrate composite sync to -2
Vp-p min pulse. For
N.T.S.C. sync, Vert. sync C-u"
1.4 M 10-4
Vertical sync coupling capacitor.
VB.G.pk = VFLYBACK
VSAW p-p 'd"--'
(Comp. sync) Vp-p
Vertical Retrace timing resistor.
Component
Typical
1000 pF
Comments
Vertical Retrace timing capacitor,
works with Rt to determine ON
time of vertical ramp switch at
pin 12.
tv. RETRACE E 0.75 Ric, sec.
Oscillator phase shift resistor.
Works with Ro to produce 45" lag
required by VCO phase shifter.
Defines Q of ceramic resonator
tuned network, which affects
VCO control curve.
Completes VCO loop with phase
lag, required to sustain oscillation
and suppress resonator
overtones.
Series resistor to device supply
pin 9. Must supply sufficient
current to activate internal shunt
regulator.
_ V(unreg) _ 9V
Device supply decoupling
capacitor.
Horizontal pre-driver output
resistor, supplies base current to
Horizontal driver transistor when
pin 8 is OFF.
Horizontal APC loop filter high
frequency roII-off. C2 also
prevents signal on loop filter from
saturating phase detector output.
Rx, Ry and Cc form the Horizontal
APC loop filter. See Applications
Information to modify loop
parameters.
Applications Information
I. VERTICAL COUNTER
The vertical counter in the LM1880 replaces the conven-
tional vertical oscillator in a television receiver. The vertical
lock-in range is governed by the width of the vertical sync
window, which opens from count 510 to count 574 following
a vertical reset. The vertical lock frequencies are referenced
to twice horizontal frequency to insure interlaced vertical
and horizontal outputs. For fHORlZ = 15,734 Hz, the vertical
lock frequencies are calculated as follows:
2 (15,734)
fV.HlGH = -sTi'- = 61.7 Hz.
2 (15,734)
fV.LtyN = -57Ti- = 54.8 Hz.
In virtually all standard and non-standard sync signals the
vertical sync is also derived from the horizontal, so that as
long as the horizontal sync frequency is within the pull-in
range of the LM1880 (approximately i600 Hz), the vertical
lock window will remain centered on the vertical sync. Thus,
the effective vertical lock range is increased by the horizon-
tal APO:
2 (15,734 + 600) -
fV.HlGH(EFF) =
2 (15,734 - 600)
574 = 52.7 Hz.
fV.LOW(EFF) =
The time required for the vertical to "roll-thm" and lock is a
function of the difference frequency and relative phase of
fv.Low and the vertical sync:
tROLL-THRU (AVG) = 5 60 = 100 ms.
- 55 Hz
ll. HORIZONTAL APC LOOP PARAMETERS
The following information is given to provide a basis for
modifying the filter to achieve the desired loop performance.
Although the VCO is actually running at 503.5 kHz, for con-
venience all parameters are referenced to the actual hori-
zontal output frequency at pin 8.
DC Loop Gain
The DC loop gain is the product of the phase detector Gon-
version gain (p) and the VCO sensitivity (l?). For the typical
application circuit,
p. = 1.6 X 10-4RyV/Rad
B = 800 Hz/V
p.13 = 0.13 Ry Hz/Rad
for Ry = 100 kn, p3 = 13,000 Hz/Rad
In order to determine static phase error (S.P.E.), the loop
gain may be expressed in Hz/ "s:
- 13,000 A "
"B 63.5 MS
= 1,286 Hz/ps
For comparison, this value is nearly double the loop gain of
the LM1391. The increased loop gain (reduced phase error)
guarantees accurate centering of the burst gate pulse on
pin 13 of the LM1880.
The following equations cover AC loop parameters of
interest:
Nolse Bandwidth
f z 1 + 27 (RE/le) cc Ma Hz
Damping Factor
K '''-er,,.-/lcpsl?
Pull-ln Range
The pull-in and hold-in range of the LM1880 horizontal APC
loop are directly determined by the VCO control range. Thus
the loop would be capable of pulling the VCO further than
$600 Hz, but it has well defined frequency limits which pre-
vent it from doing so. As a result of these built-in "stops",
the loop parameters may be varied over a large range with-
out affecting pull-in performance.
The VCO control range, and hence pull-in, can be modified
to some extent by varying the Q of the ceramic resonator
with resistor Rs:
lncr.Rs - lncr. Pull-in
Reduce Rs -+ Reduce Pull-in
However, because of the non-linearity of the resonator, Rs
has a much greater effect on the negative side pull-in than
the positive side.
Ill. LAYOUT NOTES
Since the LM1880 uses a counter to derive the horizontal
frequency, care must be taken to prevent extraneous sig-
nals from the horizontal driver and output stages from feed-
ing back to the VCO where they could cause false counts
and consequent severe phase jitter. The following guide-
lines will prevent this problem from occuring:
A, Keep the VCO feedback capacitor, CL, as close as possi-
ble to device pins 6 and 7.
B. Limit the lead length on the horizontal output pin 8. If a
long line is required to the driver base, isolate it with a
small series resistor (200-300n) next to pin 8.
088i W1
LM1880
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Schematic Diagram
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Circuit Description (See Schematic Diagram)
The LM1880 uses a phase-shift type voltage-controlled os-
cillator (VCO). The gain for the oscillator loop is derived
from differential amplifiers Q30, 031 and Q22, 023. The
collector current in Q23 is phase-shifted 45' at pin 5 and
summed with a portion of the current in Q22, controlled by
differential amplifier Q20, 021. The resulting output phase
at pin 4 coupled through the ceramic resonator to pin 6
defines the oscillation frequency. Differential amplifier 016,
Q17, controlled by the pin 2 voltage, determines the current
split in 020 and Q21 and, consequently, the pin 4 phase
and oscillation frequency. The multiple-emitter degeneration
in 017 compensates the resonator phase characteristic to
produce a nearly linear VCO control curve,
The 503.5 kHz output of the VCO is taken from squaring
amplifier Q32, 033 through 034 and 035 to the I2L + 16
pre-scaler T0-T3. The 21.4 output is then divided again in T4
to produce the desired horizontal frequency at gate GB. The
horizontal pre-driver section consists of Q3, 04 and Q5,
which produce an open-tnl-or output square~wave at
pin 8.
The tttH pre-scalar output also drives a data flip-tlop which
resets the vertical counter FI-FO, The data input of the
reset flip-flop is controlled by the vertical sync from pin 10
subject to gates G3 and G5. After 510 21H cycles following
reset, vertical sync from 01 and G4 is enabled by 63. A
sync pulse received after this time initiates reset on the next
21H cycle. If no pulse is received after 542 cycles. G5 will
initiate the reset process. A reset pulse from the counter is
taken via G9 to the retrace timing section. SCR 08, 09 is
normally ON, holding a capacitor on pin 11 near ground.
During this time Q11 and 012 are OFF, allowing the vertical
ramp to form on pin 12. When the reset pulse is received,
Q7 turns Q8, 09 OFF and 011, 012 ON, discharging the
vertical ramp for the duration of the retrace time. Retrace is
completed when the pin 11 capacitor charges to the 08
threshold, and the SCR again latches.
The remaining sections of the device are the horizontal
phase detector and burst gate former. The balanced phase
detector consists of comparator 043. Q44 and current
source Q39 gated by differential amplifier 041. 042. Nega-
tive horizontal sync pulses on pin 14 enable the comparator,
and the flyback sawtooth on pin 1 switches the current from
Q43 to Q44 based on the relative phase between the sync
and sawtooth. Q44 takes a (-) current pulse from pin 2,
while the pulse in Q43 is turned around in the current mirror
Q45, 046 and Q47 to produce a (+) current pulse at pin 2.
These currents are then integrated by the external loop filter
to control the VCO.
The flyback sawtooth also switches differential amplifier
Q49, 050, which activates the burst gate. During the first
half of the flyback pulse 049 will be ON, which turns 051
and 052 ON and clamps pin 13 near ground. The sawtooth
switches Q49, 051 and 052 OFF at the peak of the flyback,
releasing pin 13. In this manner, the second halt ofa flyback
pulse ted to pin 13 can be used as a burst gate.
053, 054 and 055 form the active shunt regulator which
holds the supply pin 9 at 8.7V typ.
OBBLW'I
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