LFTVS10-1F3 ,Transil™, transient voltage suppressorPin configuration (bump side)■ RoHS compliantA BComplies with the following standards:■ IEC 61000-4 ..
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LFTVS10-1F3
Transil™, transient voltage suppressor
November 2008 Rev 1 1/7
LFTVS10-1F3 ransil™, transient voltage suppressor
Features Transient voltage suppressor Electrostatic discharge protection Electrical overstress protection Unidirectional device Low clamping factor VCL/VBR Fast response time Very thin package: 0.605 mm RoHS compliant
Complies with the following standards: IEC 61000-4-2 level 4 ± 15 kV (air discharge) ± 8 kV (contact discharge)
DescriptionThe LFTVS10-1F3 is a single line diode designed
specifically for the protection of integrated circuits
in portable equipment and miniaturized electronic
devices subject to ESD and EOS transient
overvoltages.
Figure 1. Pin configuration (bump side)
Figure 2. Device configuration
TM: Transil is a trademark of STMicroelectronics
Characteristics LFTVS10-1F32/7
1 Characteristics
Table 1. Absolute maximum ratings (Tamb = 25 °C)
Table 2. Electrical characteristics (Tamb = 25 °C) 8 / 20 µs pulse waveform DC current not recommended for more than 5 s. Even if diode failure mode is short circuit the bumps could
exceed melting temperature and the component disassembled from the board.
LFTVS10-1F3 Characteristics 3/7
Figure 3. Relative variation of peak pulse
power versus initial junction
temperature
Figure 4. Peak pulse power versus
exponential pulse duration (typical
value)
Figure 5. Clamping voltage versus peak
pulse current (typical values)
Figure 6. Relative variation of leakage
current versus junction
temperature (typical values)
Figure 7. Forward voltage drop versus peak
forward current (typical values)
Figure 8. Junction capacitance versus line
voltage (typical values)
Ordering information scheme LFTVS10-1F34/7
Figure 9. Breakdown voltage versus initial junction temperature (typical value) Ordering information scheme
Figure 10. Ordering information scheme
5/7
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
.
Figure 11. Flip Chip dimensions
Figure 12. Footprint recommendations Figure 13. Marking
Ordering information LFTVS10-1F36/7
Figure 14.Note: More information is available in the application notes:
AN2348: “400 µm flip chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
4 Ordering information
5 Revision history
Table 3. Ordering information
Table 4. Document revision history
