LF6197CCJ ,160 ns Monolithic Sample-and-Hold AmplifierFeaturesYOperates with supply voltages fromg5V tog18VTheLF6197isamonolithicsample-and-hold(S/H)ampl ..
LF80AB ,VERY LOW DROP VOLTAGE REGULATORS WITH INHIBITELECTRICAL CHARACTERISTICS FOR LF12C (refer to the test circuits, T =25°C, C =0.1 µF,j IC =2.2 µ F ..
LF80ABDT-TR ,VERY LOW DROP VOLTAGE REGULATORS WITH INHIBITELECTRICAL CHARACTERISTICS FOR LF12AB (refer to the test circuits, T =25°C,C =0.1 µF,j IC =2.2 µ F ..
LF80ABPT ,VERY LOW DROP VOLTAGE REGULATORS WITH INHIBITABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Input Voltage-0.5 to 40 (*) VII Output Curr ..
LF80CDT-TR ,VERY LOW DROP VOLTAGE REGULATORS WITH INHIBITLF00SERIESVERY LOW DROPVOLTAGE REGULATORS WITH INHIBIT
LF6197CCJ
160 ns Monolithic Sample-and-Hold Amplifier
TL/H/11381
LF6197
Monolithic
Sample-and-Hold
Amplifier
September 1992
LF6197 160 ns Monolithic Sample-and-Hold Amplifier
General Description
The LF6197isa monolithic sample-and-hold (S/H) amplifier
that usesa proprietary ‘‘current-multiplexed sample-and-
hold’’ techniqueto offer extremely high speed while main-
taining12bitsor higher accuracy.The deviceis built using
National’s advanced junction-isolated VIPTM (Vertically Inte-
grated PNP)and BI-FETTM process technologies.
The LF6197 acquiresa10V step inputto within g0.01%in
160nsand has10mV hold step error when going from
sample tohold mode.The input offset voltageinthe sample
modeis typically3 mV. Evenat extremely fast acquisition
speeds,no compromisesare madeinthe droop rate, which0.6 mV/ms. When configuredfor unity gain,theDC gain
erroris 0.03%. The feedthrough attenuationinthe hold
modeis83dBatDCand77dBat 100 kHz.
The LF6197canbe externally configuredfor either inverting non-inverting gains, thus offering additional flexibilityto
the user.The device includesan internal10 pFhold capaci-
tor.
BI-FETTMandVIPTMare trademarks ofNationalSemiconductor Corporation.
Features Operates with supply voltages from g5Vto g18V CMOS, TTLand ECL compatible logic input Adjustable invertingor non-inverting gain Internal hold capacitor High power-supply rejectionin both sample and hold
modes
Key Specifications Acquisition time (10V stepto 0.01%) 160ns Hold mode settling time (10V stepto 0.01%) 50ns Droop rate 0.6 mV/ms Hold step 10mV Aperture jitter 8 psrms Feedthrough attenuationatDC 83dB Small signal bandwidth 25 MHz
Applications High-speed data acquisition systems Automatictest equipment High-speed instrumentation Replaces expensive hybrid sample-and-hold amplifiers
Block Diagram
TL/H/11381–1
Connection Diagram
TL/H/11381–2
TopView
Ordering Information
Industrial Package(0§Ck TAk a70§C)
LF6197CCJ J14A
CeramicDIP
C1995National SemiconductorCorporation RRD-B30M115/PrintedinU.S.A.
