LF353D ,JFET input operational amplifierMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
LF353DG4 ,Dual General-Purpose JFET-input Operational Amplifier 8-SOIC 0 to 70Features... 18.4 Device Functional Modes...... 82 Applications..... 19 Application and Implementati ..
LF353DR ,Dual General-Purpose JFET-input Operational AmplifierTable of Contents8.3 Feature Description...... 81
LF353DR2 ,Quad Operational Amplifier, Internally Compensated, JFET InputMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V +18 VCCN SUFFIXV –18EE PLASTIC PACKAGECASE ..
LF353DR2 ,Quad Operational Amplifier, Internally Compensated, JFET InputOrder this document by LF347/D ** ** *FAMILY OF JFETThese low cost JFET input operational amplifie ..
LF353DR2 ,Quad Operational Amplifier, Internally Compensated, JFET InputMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V +18 VCCN SUFFIXV –18EE PLASTIC PACKAGECASE ..
LM1871N ,RC Encoder/Transmitterapplicationsthe temperature range extremes are +130˚C and −55˚C.Decreasing the power supply voltage ..
LM1872 ,Radio Control Receiver/Decoderapplications. The device is well suited for use at ei-Yther 27 MHz, 49 MHz or 72 MHz in controlling ..
LM1875 ,20-W Audio Power Amplifierapplications. YLow distortion: 0.015%, 1 kHz, 20 WYThe LM1875 delivers 20 watts into a 4X or 8X loa ..
LM1875 ,20-W Audio Power AmplifierApplicationspower bandwidth, large output voltage swing, high currentYHigh performance audio system ..
LM1875 ,20-W Audio Power AmplifierApplicationsTL/H/5030–1FrontViewOrderNumberLM1875TSeeNSPackageNumberT05BTL/H/5030–2C1995NationalSem ..
LM1875T ,20-W Audio Power AmplifierElectrical CharacteristicsV =+25V, −V =−25V, T =25˚C, R =8Ω,A =20 (26 dB), f =1 kHz, unless otherwi ..
LF353D
JFET input operational amplifier
Product Preview
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Registered OutputsThe MCM67J618B is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive registered output drivers onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered non-
inverting registers.
This device contains output registers for pipeline operations. At the rising edge
of K, the RAM provides the output data from the previous cycle.
Output enable (G) is asynchronous for maximum system design flexibility.
Burst can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM67J618B (burst sequence imitates that of the
i486) and controlled by the burst address advance (ADV) input pin. The following
pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
This device is ideally suited for systems that require wide data bus widths and
cache memory. See Figure 2 for applications information. Single 5 V ± 5% Power Supply Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Output Registers for Pipelined Applications Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package ADSP Disabled with Chip Enable (E) — Supports Address Pipelining
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
PIN ASSIGNMENTDQ9
VCC
DQ8
DQ6
DQ7
VSS
DQ4
DQ5
DQ2
DQ3
VSS
VCC
DQ0
DQ1
VCC
VSS
VSS
VCC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17A7EUW K A8A9A10LW ADV GADSCADSP
A15A3A2
A13A14 A12 A0
Order this document
by MCM67J618B/D-
SEMICONDUCTOR TECHNICAL DATAAll power supply and ground pins must be
connected for proper operation of the device.
