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LD1117AD2MTR-LD1117ADT25-LD1117ADTTR-LD1117ADT-TR-LD1117AS12TR-LD1117ASTR
LOW DROP FIXED AND ADJUSTABLE POSITIVE VOLTAGE REGULATORS
1/17October 2004 LOW DROPOUT VOLTAGE
(1.15V TYP. @ IOUT = 1A, 25°C) VERY LOW QUIESCENT CURRENT
(5 mA TYP. @ 25°C) OUTPUT CURRENT UP TO 1A FIXED OUTPUT VOLTAGE OF: 1.2V, 1.8V,
2.5V, 2.85V, 3.3V, 5.0V ADJUSTABLE VERSION AVAILABILITYrel = 1.25V) INTERNAL CURRENT AND THERMAL LIMIT ONLY 10 µF FOR STABILITY AVAILABLE IN ± 2% (AT 25°C) AND 4% IN
FULL TEMPERATURE RANGE HIGH SUPPLY VOLTAGE REJECTION:
(80dB TYP. AT 25°C) TEMPERATURE RANGE: 0°C TO 125°C
DESCRIPTION The LD1117A is a LOW DROP Voltage Regulator
able to provide up to 1A of Output Current,
available even in adjustable version (Vref=1.25V).
Concerning fixed versions, are offered the
following Output Voltages: 1.2V, 1.8V, 2.5V,
2.85V, 3.3V and 5.0V. The 2.85V type is ideal for
SCSI-2 lines active termination. The device is
supplied in: SOT-223, DPAK and TO-220. The
surface mount packages optimize the thermal
characteristics even offering a relevant space
saving effect. High efficiency is assured by NPN
pass transistor. Only a very common 10µF
minimum capacitor is needed for stability. Only
chip trimming allows the regulator to reach a very
tight output voltage tolerance, within ± 2% at 25°C.
LD1117A
SERIES LOW DROP FIXED AND ADJUSTABLE
POSITIVE VOLTAGE REGULATORS
Figure 1: Block DiagramRev. 12
LD1117A SERIES2/17
Table 1: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied. Over the above suggested Max Power Dissipation a Short Circuit could definitively damage the device.
Table 2: Thermal Data
Figure 2: Pin Connection (top view) NOTE: The TAB is connected to the VOUT.
Table 3: Order Codes
LD1117A SERIES3/17
Figure 3: Application Circuit (For Other Fixed Output Voltages)
Table 4: Electrical Characteristics Of LD1117A#12 (refer to the test circuits, TJ = 0 to 125°C, CO = 10
µF, C I = 10 µF, R = 120 Ω between OUT-GND, unless otherwise specified)
LD1117A SERIES4/17
Table 5: Electrical Characteristics Of LD1117A#18 (refer to the test circuits, TJ = 0 to 125°C,O = 10 µF, CI = 10 µF unless otherwise specified)
Table 6: Electrical Characteristics Of LD1117A#25 (refer to the test circuits, TJ = 0 to 125°C,
CO = 10 µF, C I = 10 µF unless otherwise specified)
LD1117A SERIES
5/17
Table 7: Electrical Characteristics Of LD1117A#28 (refer to the test circuits, TJ = 0 to 125°C,O = 10 µF, CI = 10 µF unless otherwise specified)
Table 8: Electrical Characteristics Of LD1117A#33 (refer to the test circuits, TJ = 0 to 125°C,
CO = 10 µF, C I = 10 µF unless otherwise specified)
LD1117A SERIES
6/17
Table 9: Electrical Characteristics Of LD1117A#50 (refer to the test circuits, TJ = 0 to 125°C,O = 10 µF, CI = 10 µF unless otherwise specified)
Table 10: Electrical Characteristics Of LD1117A (Adjustable) (refer to the test circuits, TJ = 0 to
125°C, CO = 10 µF, C I = 10 µF unless otherwise specified)
LD1117A SERIES
7/17
TYPICAL APPLICATIONS
Figure 4: Negative Supply
Figure 5: Active Terminator for SCSI-2 BUS
Figure 6: Circuit for Increasing Output Voltage
LD1117A SERIES
8/17
Figure 7: Voltage Regulator With Reference
Figure 8: Battery Backed-up Regulated Supply
LD1117A SERIES
9/17
Figure 9: Post-Regulated Dual Supply
LD1117A ADJUSTABLE: APPLICATION NOTE
The LD1117A ADJUSTABLE has a thermal
stabilized 1.25±0.012V reference voltage between
the OUT and ADJ pins. I ADJ is 60µA typ. (120µA
max.) and ΔI ADJ is 1µA typ. (5µA max.).
R1 is normally fixed to 120Ω. From figure 7 we
obtain: OUT = V REF + R2 (IADJ + IR1 ) = V REF + R2 (I ADJ+VREF /R1) = VREF (1 + R2 / R1) + R2 x IADJ.
In normal application R2 value is in the range of
few Kohm, so the R2 x IDJ product could not be
considered in the VOUT calculation; then the
above expression becomes: OUT = V REF (1 + R2 / R1).
In order to have the better load regulation it is
important to realize a good Kelvin connection of
R1 and R2 resistors. In particular R1 connection
must be realized very close to OUT and ADJ pin,
while R2 ground connection must be placed as
near as possible to the negative Load pin. Ripple
rejection can be improved by introducing a 10µF
electrolytic capacitor placed in parallel to the R2
resistor (see Fig. 10).
