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L9997ND ,DUAL HALF BRIDGE DRIVERELECTRICAL CHARACTERISTICS (7V < V < 16.5V; -40°C < T < 150°C; unless otherwise specified.)S JSymbo ..
L9997ND013TR ,DUAL HALF BRIDGE DRIVERELECTRICAL CHARACTERISTICS (7V < V < 16.5V; -40°C < T < 150°C; unless otherwise specified.)S JSymbo ..
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L9958SB-L9958XP-L9958XPTR
SPI Controlled H-Bridge
December 2013 DocID17269 Rev 6 1/38
L9958Low R DSON SPI controlled H-Bridge
Datasheet - production data
Features Programmable current regulation peak
threshold by SPI up to 8.6 A typ. Operating battery supply voltage 4.0 V to 28 V Operating Vdd supply voltage 4.5 V to 5.5 V All pins withstand 19 V, Vs and output pins
withstand 40 V Full path Ron from 100 mΩ (at Tj = -40 °C) to
300 mΩ (at Tj =150 °C) Logic inputs TTL/CMOS-compatible Operating frequency up to 20 kHz 16-bit SPI interface for
configuration/diagnostics, daisy chain capability Over temperature and short circuit protection VS undervoltage disable function Vdd undervoltage and overvoltage protection Vdd overvoltage detection Open-load detection in ON condition Full diagnostics in OFF state Enable and disable input Low stand by current (<10 μA) Voltage and current slew-rate control for low EMI, programmable through SPI Available in three power packages
DescriptionThe L9958 is an SPI controlled H-Bridge,
designed for the control of DC and stepper motors
in safety critical applications and under extreme
environmental conditions.
The H-Bridge is protected against over
temperature, short circuits and has an
undervoltage lockout for all the supply voltages Vs
and Vdd, and for overvoltage on Vdd. All
malfunctions cause the output stages to go
tristate.
Detailed failure diagnostics on each channel is
provided via SPI: short circuit to battery, short
circuit to ground, short circuit overload, over
temperature.
Open-load can be detected in ON condition, for
the widest application ranges. Current regulation
threshold can be set by SPI from 2.5 A to 8.6 A
(Typ.), in 4 steps. Guaranteed accuracy is ±10 %
on all temp range, using an external reference
resistor with 1% accuracy over all temp range.
Current limitation threshold is linearly reduced by
temperature over 165 °C.and a thermal warning
bit is set by SPI. The H-Bridge contains integrated
free-wheel diodes. In case of free-wheeling
condition, the low side transistor is switched on in
parallel of its diode to reduce power dissipation.
A multiple wire bonding technique, as well as ST
proprietary package design is making L9958
compatible with three power packages, for
maximum flexibility:
PowerSO-20 package (medium power, JEDEC
standard MO166);
PowerSO16 package (medium power, lower
cost);
PowerSSO24 package (low power, very low cost
JEDEC standard MO271A).
Table 1. Device summary
Order code Package PackingL9958 PowerSO-20 Tube
L9958SB PowerSO16 Tube
L9958XP PowerSSO24 Tube
Contents L99582/38 DocID17269 Rev 6
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 PowerSO-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 PowerSO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 PowerSSO24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1 DI and EN inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.2.2 DIR and PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1 Daisy chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 SPI communication failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 5 V and 3.3 V output compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1 Temperature-dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Current regulation with low-inductive loads . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Slew rate control in case of current limitation on low-side . . . . . . . . . . . . 17
Diagnostics and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195.1 Diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Reset requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1.2 Diagnosis reset bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2 Protection and on state diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2.1 Over-current on high-side - short to ground . . . . . . . . . . . . . . . . . . . . . .20
5.2.2 Over-current on low-side - short to Vs . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2.3 Short circuit over-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2.4 Open load in on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2.5 Over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
DocID17269 Rev 6 3/38
L9958 Contents5.2.6 Vs under-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.2.7 Vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.2.8 Vdd under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.2.9 Output short protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
5.3 Off-state diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3.1 Off-state detection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.3.2 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.4 H-Bridge functional status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.4.2 Device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
6.4.3 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.4.4 Digital inputs: TTL // 3.3V / 5V CMOS compatible . . . . . . . . . . . . . . . . .29
6.4.5 Bridge output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6.4.6 Over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
6.4.7 Current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . .30
6.4.8 Diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.4.9 Off-state diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
6.4.10 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
List of tables L9958
4/38 DocID17269 Rev 6
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2. PowerSO-20 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. PowerSO16 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 4. PowerSSO24 pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 5. Control pins EN, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. Control pins DIR, PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 7. Configuration protocol (CFG_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8. Diagnosis protocol (DIA_REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. Current limitation programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 10. Slew rate control on low side MOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Table 11. Diagnosis reset strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 12. Over-temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 13. Vs under-voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 14. Vdd over-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 15. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 16. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 17. Range of functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 18. Device supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 19. Device supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Table 20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 21. Digital inputs: TTL // 3.3V / 5V CMOS compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 22. Bridge output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 23. Over-temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 24. Current limitation and over-current detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 25. Diagnostic of open-load in on-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 26. Off-state diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 27. Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 28. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
DocID17269 Rev 6 5/38
L9958 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 2. PowerSO-20 pin connection (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. PowerSO16 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Figure 4. PowerSSO24 pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Figure 5. H-Bridge configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 6. SPI protocol structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 7. FSI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 8. Daisy chain topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 9. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 10. SPI zero clock communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 11. Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 12. Temperature dependent current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 13. Current regulation with different loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 14. Slew rate switching strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 15. Diagnostics for SCB / SCOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 16. Open load in on state - Low-side current recirculation . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 17. Battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 18. Off-state detection scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 19. Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 20. Off-state diagnostic principle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 21. Thermal impedance (junction-ambient) of power packages . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 22. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 23. PowerSO-20 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 24. PowerSO16 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 25. PowerSSO24 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . .36
Block diagram L9958
6/38 DocID17269 Rev 6
1 Block diagram
Figure 1. Block diagram
DocID17269 Rev 6 7/38
L9958 Pins description
2 Pins description
2.1 PowerSO-20
The exposed slug must be soldered on the PCB and connected to GND.
Figure 2. PowerSO-20 pin connection (top view)
Table 2. PowerSO-20 pin function
Pin N° Name Description GND Ground SO Serial out VDDIO Supply voltage for SPI CS Chip select CP Charge pump VS Supply voltage DIR Direction input OUT1 Output 1 DI Disable GND Ground GND Ground EN Enable OUT2 Output 2 PWM PWM input REXT External reference resistor SI Serial in SCK SPI clock VDD Supply voltage N.C. Not connected (To be connected to GND on the PCB) GND Ground
Pins description L9958
8/38 DocID17269 Rev 6
2.2 PowerSO16
The exposed slug must be soldered on the PCB and connected to GND
Figure 3. PowerSO16 pin connection (top view)
Table 3. PowerSO16 pin function
Pin Nº Name Description GND Ground SO Serial Out CS Chip Select CP Charge pump DIR Direction Input OUT1 Output 1 DI Disable PGND Power Ground EN Enable OUT2 Output 2 PWM PWM Input REXT External Reference Resistor VS Supply Voltage SI Serial In SCK SPI Clock VDD Supply Voltage
DocID17269 Rev 6 9/38
L9958 Pins description
2.3 PowerSSO24
Although this package has two separate pins for the ground (pin 11 = PGND = Power
Ground and pin 22 = GND = Logic Ground), the device is designed to work with shortening
ground and is mandatory that the two pins have to be connected nearby the IC on the PCB.
The exposed slug must be soldered on the PCB and connected to GND.
Figure 4. PowerSSO24 pin connection (top view)
Table 4. PowerSSO24 pin function
Pin Nº Name Description
1, 2, 12, 13,
14, 23, 24 N.C. Not Connected SO Serial Out VDDIO Supply Voltage for SPI CS Chip Select CP Supply Voltage for SPI VS Supply Voltage DIR Direction Input OUT1 Output 1 DI Disable PGND Power Ground EN Enable OUT2 Output 2 PWM PWM Input REXT External Reference Resistor SI Serial In SCK SPI Clock VDD Supply Voltage GND Ground
Device description L9958
10/38 DocID17269 Rev 6
3 Device description
3.1 Supply range
The L9958 has an operating supply range from "Vs_uv" (battery monitoring) up to 28 V.
However, the device is tested until 16 V; the functionality of the device is guaranteed until V. The absolute maximum rating is defined to 40 V DC.
3.2 Control inputs
The bridge is controlled by the Inputs PWM, DIR, EN and DI.
All the digital inputs and outputs of the L9958 are compatible with 3.3 V and 5 V CMOS. The
power stages output OUT1 and OUT2 are controlled by the direct inputs DIR and PWM as
given in Table 5. The DIR input gives the direction of output current, while the PWM input
controls whether the current is increased or reduced.
3.2.1 DI and EN inputs
The pin DI is internally pulled-up and high active. When DI is active (set to HIGH), the bridge
is set to tristate, whatever the state of the DIR and PWM inputs. All the data stored in SPI
registers are not reset and SPI communication with the MCU is still possible. When DI is
inactive (set to LOW), the bridge is controlled by the DIR and PWM inputs.
The pin EN is internally pulled down and high active. When EN is inactive (set to LOW), the
bridge is set to tri-state, whatever the state of the DIR and PWM inputs. All the data stored in
SPI registers are not reset and SPI communication with the MCU is still possible. When EN
is active (set to HIGH), the bridge is controlled by the DIR and PWM inputs. The coding is
performed as shown in the next table. The state of the bridge is transferred in the diagnostic
register in a bit called "ACT".
Table 5. Control pins EN, DI DI Bit “ACT” Bridge status 0 0 Tri-state 1 0 Tri-state 0 1 On-state 1 0 Tri-state
DocID17269 Rev 6 11/38
L9958 Device description
3.2.2 DIR and PWM inputs
The pins DIR and PWM are internally pulled down. The bridge is controlled by these two
inputs according to the table below.
Figure 5. H-Bridge configurations
The outputs can be disabled (set to tri-state) by the Disable and Enable inputs DI and EN.
Input DI has an internal pull-up. Input EN has an internal pull-down. During freewheeling
phase, an active freewheeling on the Low-Side MOS is automatically set, switching ON the
power transistor in parallel to the internal freewheeling diode.
Table 6. Control pins DIR, PWM
DIR PWM OUT1 OUT2 Bridge Status H H L Forward L L L Freewheeling Low H L H Reverse L L L Freewheeling low
Device description L9958
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3.3 Serial peripheral interface (SPI)
The SPI is used for bidirectional communication with a control unit, allowing IC
configuration, diagnosis and identification. L9958 can also be used in daisy-chain
configuration (number of device in the daisy chain is not limited).
The SPI interface of L9958 is a slave SPI interface: the master is the μC which provides CS
and SCK to L9958.
Transfer format uses 16 bits word in case of single device configuration and multiple of 16
bits word in case of daisy chain configuration.
The first answer after Power-ON-Reset is the IC identifier.
A command sent by the μC during transfer N is answered during transfer N+1. SO is
clocked on SCK rising edge. SI is sampled on falling edge. When CS = '1' and during power-
ON reset, SO is in tri-state. Otherwise, the SPI interface is always active.
Settings made by the SPI control word become active at the end of the SPI transmission
and remain valid until a different control word is transmitted or a power on reset occurs.
At each SPI transmission, the diagnosis bits as currently valid in the error logic are
transmitted. Details on diagnosis are described in Section 5.
Figure 6. SPI protocol structure
Between CS falling edge and SCK rising edge, an internal signal called "FSI bit" is set
asynchronously on SO output. This can be useful to have internal information on the device
without stimulating the SCK clock. The definition of the FSI bit is presented in the
diagnostics chapter.
Figure 7. FSI bit
Except the Enable / Disable bit (“ACT” pin), all the bits of diagnosis register are latched and
can be released by: Diagnosis register read by SPI Power-On-Reset condition.
The coding for the Configuration and Diagnosis Registers is reported in the table below.
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L9958 Device description
Table 7. Configuration protocol (CFG_REG)
Bit Name Description Config. value
after reset
0 - LSB RES Reserved — DR Diagnostic Reset Bit 0 CL_1 Bit1 for Regulation Current Level 0 CL_2 Bit2 for Regulation Current Level 1 RES Reserved — RES Reserved — RES Reserved — RES Reserved — VSR Voltage Slew Rate Control Value 0 ISR Current Slew Rate Control Value 0 ISR_DIS Current Slew Rate Control Disable 0 OL_ON Open Load in ON state Enable 0 RES Reserved — RES Reserved — 0 “0” to be written —
15-MSB 0 “0” to be written —
Table 8. Diagnosis protocol (DIA_REG)
Bit Name Description Status after
reset Bit state DR impact H-bridge
status
0-LSB OL_OFF Open Load in OFF condition 0 Latched – – OL_ON Open Load in ON condition 0 Latched – – VS_UV Vs undervoltage 0 Not latched – Hi-Z if “1” VDD_OV Vdd overvoltage 0 Latched X Hi-Z if “1” ILIM Current Limitation reached 0 Latched – – TWARN Temperature warning 0 Latched – – TSD Over-temperature Shutdown 0 Latched X Hi-Z if “1” ACT Bridge enable 1 Not latched – Hi-Z if “0” OC_LS1 Over-Current on Low Side 1 0 Latched X Hi-Z if “1” OC_LS2 Over-Current on Low Side 2 0 Latched X Hi-Z if “1” OC_HS1 Over-Current on High Side 1 0 Latched X Hi-Z if “1” OC_HS2 Over-Current on High Side 2 0 Latched X Hi-Z if “1” Null Not Used – – – – Null Not Used – – – – SGND_OFF Short to GND in OFF condition 0 Latched – –
15-MSB SBAT_OFF Short to Battery in OFF condition 0 Latched – –
Device description L9958
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3.3.1 Daisy chain operation
Several L9958 can be connected to one SPI connection in daisy chain operation to save μC
interface pins. The number of devices connected in daisy chain is unlimited.
Figure 8. Daisy chain topology
3.4 SPI timing
Figure 9. SPI timing
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L9958 Device description
3.5 SPI communication failure
In case of "no SCK edge" when CS = '0', the transfer is considered as valid: no error is
returned to the μC. The answer of last command is sent during next transfer.
When the number of SCK period is different from 0 or multiple of 16, next SPI answer is all
zero.
Figure 10. SPI zero clock communication
3.6 5 V and 3.3 V output compatibility
In order to ensure a full compatibility with 5V and 3.3V MCU peripherals, the pin VDDIO is
dedicated to supply the output buffer of SO. The overall current consumption on Vddio is
"Ivddio". A parasitic current from the pin SO could flow through the pin VDDIO in case of
over-voltage on SO pin vs. VDDIO pin.
Current regulation L9958
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4 Current regulation
To protect the actuator and limit power dissipation, a two-level chopper current limitation is
integrated as shown in figure below. The current is measured by sense cells integrated in
the low-side switches. As soon the upper current limit “IH” is reached, both low-side drivers
are switched on to allow free-wheeling recirculation, until the lower current limit “IL” is
reached. During the current regulation, all the slew rate controls are disabled in order to
minimize the power dissipation. Four current limit levels can be set by the SPI control bits 0
and 1. In order to achieve very precise current threshold and ripple, an external resistance is
required (1 % accuracy on all temp range/lifetime) to generate a current reference. Detailed
values for current thresholds and ripple are reported in Table 9.
Figure 11. Current limitation
4.1 Temperature-dependent current regulation
In order to reduce power dissipation and thus the junction temperature, above a
temperature Twarn = 160 °C, current regulation high limit linearly decreases with
temperature, to reach about 2.5 A at Tsd = 175 °C (shutdown temperature).
When this thermal threshold is reached during a current limitation phase, the information is
stored and latched in a coding of bits called "Twarn". This bit can be reset only if the settings
conditions (Tj > Twarn and ILIM = 0) are not present anymore. This feature is mainly used to
reduce the power dissipation and thus the junction temperature.
Table 9. Current limitation programmability
CL_2 CL_1 Current limit (typical values)
0 0 2.5 A
0 1 4 A 0 6.6 A (default value)
1 1 8.6 A
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L9958 Current regulation
Figure 12. Temperature dependent current regulation
4.2 Current regulation with low-inductive loads
Each time output stages are turned off, an internal timing starts for duration Toff-min.
Whenever turn-on is reached in a time Toff that is shorter than Toff-min, output stages are
kept OFF, until Toff-min is reached.
In such case the ripple control could be not so precise as specified.
Figure 13. Current regulation with different loads
4.3 Slew rate control in case of current limitation on low-side
The slew rate control can be done on voltage and current or only on voltage. This can be
selected by SPI through the bit ISR_DIS.
The slew rate of each high-side power transistor of the bridge is controlled either during
turn-on and turn-off (current AND voltage slew rate). The same setting is applied for both
switching. Moreover, this slew rate is configurable by SPI in order to get the best trade-off
between conducted/radiated EMI and power dissipation during switching. The slew rate
Current regulation L9958 DocID17269 Rev 6
selection can be done "on the fly" by SPI. The corresponding bits are called "VSR" and
"ISR". No external component is needed to select the slew rate range. Only the power
transistors not used for freewheeling can be adjusted, the two others can be controlled with
a preset slew rate.
The couples of value defined to fulfill most of the application requirements are described in
the table below. The required accuracy is ±50 % for an output current from 1A to 8A and
with output voltage up to 19 V. The overall delay implemented between high-side and low-
side transistor switching must be adjusted automatically to avoid any cross-conduction
through one half-bridge in all conditions.
In case of current limitation and any detection that put the bridge in tri-state, the slew rate is
not related anymore to the preset bits "VSR"; "ISR" but to a dedicated faster slew rate
control named "SUPER FAST" mode. The automatic change from SPI selectable to SUPER
FAST slew rate is described hereafter.
Figure 14. Slew rate switching strategy
Table 10. Slew rate control on low side MOS
Range VSR ISR dV/dt (V/μs) dI/dt (A/μs)
1 (default value)0 0 4 3 0 1 4 0.3 0 2 3 1 1 2 0.3
No SR control Not selectable 14 14
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L9958 Diagnostics and protections Diagnostics and protections
A detailed diagnostic of the H-bridge is available through SPI communication. The 16 bits
diagnostic word is sent back to the MCU in return of a command word. The diagnostic word
is used to report two kinds of information: H-Bridge failures: Over-current on each transistor in on-state, Vps under-voltage, Vdd over-voltage, Over-temperature, Open-load in on-state, Off-state diagnostic. H-bridge functional status: Current limitation condition, Current limitation decreasing condition, Disable / Enable status.
5.1 Diagnosis reset strategy
5.1.1 Reset requests
Except "ACT" and "VS_UV" bits, all the others are latched and can only be released by: Transition from "Disable" to "Enable" on DI / EN pins, Diagnostic register read by SPI (see details on each failure release) depending on bit
"DR", Power-On-Reset condition.
When the diagnostic register is reset, the bridge is switched back to normal mode driven by
DIR and PWM. All the settings are kept as before the failure. In case of SPI read, no
additional action on DI / EN is needed.
5.1.2 Diagnosis reset bit
In case of "DR" set to LOW (default value), all the bits of the diagnostic register can be reset
by the three possibilities described in previous section.
In case of "DR" set to HIGH, the over-current, Vdd over-voltage and over-temperature
diagnostic bits can NOT be reset by SPI read and therefore, the bridge is kept in tri-state
until a transition from "Disable" to "Enable" on DI/EN pins or Power-on-Reset condition.
Table 11. Diagnosis reset strategy
DR Diagnosis reset strategy All diagnostic bits reset at each SPI reading (Default) Over current bits (8..11) + Temp. shutdown TSD bit (6) + Vdd over voltage bit (3) NOT
reset by SPI
