L9950-L9950TR-L9950-TR Fast Delivery |IC PHOENIX CO.,LIMITED

L9950 ,DOOR ACTUATOR DRIVERL9950DOOR ACTUATOR DRIVER1
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L9950-L9950TR-L9950-TR
DOOR ACTUATOR DRIVER
1/23
L9950
July 2004
1FEATURES One full bridge for 6A load (ron = 150mΩ ) Two half bridges for 3A load (ron = 300mΩ ) Two half bridges for 1.5A load (ron = 800mΩ ) One highside driver for 6A load (ron = 100mΩ ) Four highside drivers for 1.5A load (ron = 800 mΩ ) Programmable Softstart function to drive loads
with higher inrush currents (i.e. current
>6A,>3A,>1.5A) Very low current consumption in standby mode
IS < 6µA, typ. Tj ≤ 85 °C) All outputs short circuit protected Current monitor output for 300mΩ ,150mΩ and
100m highside drivers All outputs over temperature protected Open load diagnostic for all outputs Overload diagnostic for all outputs Seperated half bridges for door lock motor PWM control of all outputs Charge Pump output for reverse polarity
protection APPLICATIONS
Door Actuator Driver with bridges for door lock and
safe lock, mirror axis control, mirror fold and highside
driver for mirror defroster and four 5W-light bulbs.
3DESCRIPTION
The L9950 is a microcontroller driven multifunc-
tional door actuator driver for automotive applica-
tions.Up to five DC motors and five grounded
resistive loads can be driven with six half bridges
and five highside drivers. The integrated standard
serial peripheral interface (SPI) controls all opera-
tion modes (forward, reverse, brake and high im-
pedance).
All diagnostic informations are available via SPI.
DOOR ACTUATOR DRIVER
Figure 2. Block Diagram
REV. 3
L9950
3.1 Dual Power Supply: VS and VCC
The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump
is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic
part and the SPI of the device.
Due to the independent logic supply voltage the control and status information will not be lost, if there are
temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from und-
ervoltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If
the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to
tristate (high impedance) and the status registers are cleared.
3.2 Standby-Mode
The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data Register 0. All latched
data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the
current at VS (VCC) is less than 6 µA (50µA) for CSN = high (DO in tristate). By switching the V CC voltage
a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode.
3.3 Inductive Loads
Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due
to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1
to OUT6 without external free-wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive
resistive loads. Hence only a limited energy (E<1mJ) can be dissipated by the internal ESD-diodes in free-
wheeling condition. For inductive loads (L>100µH) an external free-wheeling diode connected to GND and
the corresponding output is needed.
3.4 Diagnostic Functions
All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and ther-
mal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open load: 1ms,
respectively) before the corresponding status bit in the status registers will be set. The filters are used to
improve the noise immunity of the device. Open load and temperature warning function are intended for
information purpose and will not change the state of the output drivers. On contrary, the overload and ther-
mal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown),
respectively. Without setting the over-current recovery bits in the Input Data Register, the microcontroller
has to clear the over-current status bits to reactivate the corresponding drivers.
3.5 Overvoltage and Undervoltage Detection
If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs
OUT1 to OUT11 are switched to high impedance state to protect the load. When the voltage VS drops
below the undervoltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to
the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (in-
creased power dissipation). If the supply voltage VS recovers to normal operating voltage the outputs stag-
es return to the programmed state (input register 0: bit 20=0).
If the undervoltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deacti-
vated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set
bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery volt-
age.
3.6 Temperature Warning and Thermal Shutdown
If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI.
If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set
and power DMOS transistors of all output stages are switched off to protect the device. In order to reacti-
vate the output stages the junction temperature must decrease below Tj SD - Tj SD HYS and the thermal
shutdown bit has to be cleared by the microcontroller.
3/23
L9950
3.7 Open Load Detection
The open load detection monitors the load current in each activated output stage. If the load current is
below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in
the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs
(e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the
loads.
3.8 Over Load Detection
In case of an over-current condition a flag is set in the status register in the same way as open load de-
tection. If the over-current signal is valid for at least tISC = 32 µs, the over-current flag is set and the cor-
responding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the
over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate
the corresponding driver.
3.9 Current monitor
The current monitor output sources a current image at the current monitor output which has a fixed ratio
(1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data
Register 0 control which of the outputs OUT1, OUT4, OUT5, OUT6 and OUT11 will be multiplexed to the
current monitor output. The current monitor output allows a more precise analysis of the actual state of the
load rather than the detection of an open- or overload condition. For example this can be used to detect
the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the de-
froster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM
inputs).
3.10 PWM inputs
Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the
PWM enable bit is set, the output is controlled by the logically AND-combination of the PWM signal and
the output control bit in Input Data Register. The outputs OUT1-OUT8 and OUT11 are controlled by the
PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example,
the two PWM inputs can be used to dim two lamps independently by external PWM signals.
3.11 Cross-current protection
The six half-brides of the device are cross-current protected by an internal delay time. If one driver (LS or
HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by
the cross-current protection time. After the cross-current protection time is expired the slew-rate limited
switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on
with slew-rate limitation. Due to this behaviour it is always guaranteed that the previously activated driver
is totally turned-off before the opposite driver will start to conduct.
3.12 Programmable Softstart Function to drive loads with higher inrush currrent
Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current
of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e.
overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set,
the device will automatically switch-on the outputs again after a programmable recovery time. The duty
cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The
PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb)
until the load reaches operating condition.
The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real
overload condition can only be qualified by time. As an example the microcontroller can switch on light
bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output
will be automatically disabled if the overload condition still exits
L9950
Example of programmable softstart function for inductive loads
Figure 3.
Figure 4. Pin Connection
5/23
L9950
Table 2. Pin Description
L9950
Table 3. Absolute Maximum Ratings
Note All maximum ratings are absolute ratings. Leaving the limitation of any of these values may cause an irreversible damage of the
integrated circuit !
Table 4. Esd Protection
Note:1. HBM according to CDF-AEC-Q100-002 HBM with all unzapped pins grounded
Table 5. Thermal Data
Table 6. Temperature warning and thermal shutdown
7/23
L9950
Figure 5. Thermal Data Of Package
Table 7. ELECTRICAL CHARACTERISTICS
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
L9950
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
9/23
L9950
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
L9950 FUNCTIONAL DESCRIPTION OF THE SPI
4.1 Serial Peripheral Interface (SPI)
This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a mi-
crocontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0.
For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is
changed from the high to low transition of CLK.
This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins
and one input pin will be needed to communicate with the device. A fault condition can be detected by
setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which
is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device
without the need of a full SPI-communication cycle.
Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see FIGURE 6).
4.2 Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO)
will be in high impedance state. A low signal will activate the output driver and a serial communication can
be started. The state when CSN is going low until the rising edge of CSN will be called a communication
frame. If the CSN-input pin is driven above 7.5V, the L9950 will go into a test mode. In the test mode the
DO will go from tri-state to active mode.
Table 7. ELECTRICAL CHARACTERISTICS (continued)
(VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are
referred to GND and currents are assumed positive, when the current flows into the pin)
11/23
L9950
4.3 Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at
the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the
CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the
selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication
frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be
ignored. This safety function is implemented to avoid an activation of the output stages by a wrong com-
munication frame.
Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling
the CSN signal of the connected ICs is recommended.
4.4 Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from high impedance
to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input
after a high to low transition of the CSN pin will transfer the content of the selected status register into the
data out shift register. Each subsequent falling edge of the CLK will shift the next bit out.
4.5 Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sam-
pled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK
signal.
4.6 Input Data Register
The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input
Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of
the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data
bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO
during the current communication frame. Bit 1-17 controls the behaviour of the corresponding driver.
If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current
monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status
registers will be cleared after the current communication frame (rising edge of CSN).
4.7 Status Register
This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a
fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be
polled by the microcontroller without the need of a full SPI-communication cycle (see FIGURE 11). If one
of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of
the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal
shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear
the bit to enable the drivers.
4.8 Test Mode
The Test Mode can be entered by rising the CSN input to a voltage higher than 7.0V. In the test mode the
inputs CLK, DI, PWM1/2 and the internal 2MHz CLK can be multiplexed to data output DO for testing pur-
pose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower
current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW
and TSD thresholds.
The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched-
on at the same time. In the testmode this combination is used to multiplex the desired signals according
to following table 8:
L9950
Table 8.
Table 9. SPI - Input Data and Status Register

Partno	Mfg	Dc	Qty	Available	Descript
L9950	STM	N/a	18155	avai	DOOR ACTUATOR DRIVER
L9950TR	STM	N/a	10000	avai	DOOR ACTUATOR DRIVER
L9950-TR \|L9950TR	ST	N/a	5500	avai	DOOR ACTUATOR DRIVER