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L9848STMN/a7avaiOCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
L9848TRSTN/a5000avaiOCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER


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L9848-L9848TR
OCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
1/18
L9848

July 2003 Configurable up to 6 high side drivers RDSON=max.1.5Ω@Tj=25°C Current limit of each output at min. 0.8A Supply voltage 4.75V to 5.25V Output voltage clamping min. 35V (low side
mode) Output voltage clamping -30V (high side mode) SPI interface for data communication Additional PWM inputs for 2 outputs Thermal shutdown for all outputs Open load detection in off mode Reverse battery protection for outputs (amb) Ground disconnection for high side configured
outputs
DESCRIPTION

The L9848 IC is a highly flexible monolithic medium
current output driver that incorporates 2 dedicated
low side outputs (Outputs 7-8) and 6 outputs that can
be used as either internal low or high side drives in
any combination (Outputs 1-6). In addition, 2 outputs
are capable of being PWMed via an external pin
(Outputs 5-6). The integrated standard serial periph-
eral interface (SPI) controls all outputs and provides
diagnostic information.
Integrated clamping circuits, waveshaping, protec-
tion against positive and negative voltage transients
and thermal shutdown for all outputs open a wide
range of automotive and industrial applications
OCTAL CONFIGURABLE LOW/HIGH SIDE DRIVER
L9848
2/18
PIN DESCRIPTION
3/18
L9848
ABSOLUTE MAXIMUM RATINGS

For voltages and currents applied externally to the device. This part may be irreparably damaged if taken out-
side the specified absolute maximum rating range
(*) Internally limited
OPERATION CONDITIONS

This part may not operate if taken outside the maximum ratings. Once the condition is returned to within the
specified maximum rating or the power is re-cycled, the part will recover with no damage or degradation.
THERMAL DATA

(1) With 6cm2 on board heat sink area.
L9848
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ELECTRICAL CHARACTERISTCS
DC Characteristics

(Tj=-40°C to 150°C, VDD=4.75Vdc to 5.25Vdc, VBatt=9V to 18V, unless otherwise specified)
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L9848

* Guaranteed by design, not tested
AC Characteristics

(Tj =- 40°C to 150°C, VDD = 4.75V to 5.25Vdc, VBatt = 9V to 18V, unless otherwise specified)
ELECTRICAL CHARACTERISTCS (continued)
DC Characteristics

(Tj=-40°C to 150°C, VDD=4.75Vdc to 5.25Vdc, VBatt=9V to 18V, unless otherwise specified)
L9848
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Figure 1. DO loading for disable time measurement
Figure 2. Output loading for slew rate measurement
Figure 3. Output turn on/off delays and slew rates
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L9848
Figure 4. SPI input/output slew ratest
Figure 5. SPI timing diagram
FUNCTIONAL DESCRIPTION
General Features

The L9848 IC is a monolithic integrated circuit, which provides high flexibility for driving medium loads. 8 out-
puts, whereof 6 (Output1-6) can be used as either internal low or high side drives in any combination and 2 are
dedicated low side outputs (Output7-8). The use of this device reduces the I/O port requirements of the micro-
processor by having serially controlled outputs via a SPI interface. In addition, Output5-6 are capable of being
PWMed via an external pin (Input5-6). The 8bit SPI input is used to command the 8 output drivers either ON or
OFF and additional to indicate latched fault conditions that may have occurred. Multiple L9848s may be daisy-
chained with one additional microprocessor I/O port (CSn) for each device. The implemented self-configuration
allows the user to connect a high or low side load to any of these outputs and the L9848 will drive them correctly
L9848
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as well as provide proper fault mode operation with no other needed inputs. This device switch variable load
currents within the operation temperature range. The outputs are MOSFET drivers to minimize Vdd current re-
quirements. There's no VBatt input pin however VBatt is connected to the drains of high side outputs. The L9848
meets all required specifications when the supply voltage applied to the drain(s) of the outputs is within the op-
erating range. For supply voltages applied to the drain(s) down to 6.8V the part is functional however, it does
not meet all parametric limits, i.e. output on-state voltages.
Outputs - Common Characteristics

The 6 self-configuring outputs (Outputs1-6) are able to drive either incandescent lamps, inductive loads (non-
PWMed), or resistive loads biased to VBatt. These outputs are enabled and disabled via the SPI bus. Each of
these outputs is short circuit current limited and has an over-temperature protection as described under "Func-
tional Description - Thermal Shutdown". When a high side configured output is commanded OFF after having
been commanded ON, the source voltage will go to the lesser negative of (VBatt-45V). This is due to the design
of the circuitry and the transconductance of the MOSFET. When a low side configured output is commanded
OFF after having been commanded ON, the output voltage will rise to the internal zener clamp voltage (40Vdc
minimum) due to the flyback of the inductive load. Output 1-4
These four outputs can be used as either high or low side drives. Integrated current source pull-ups
and pull-downs are employed to correctly latch "open load" fault data. Both of these current sources
are needed to detect an open load state since these outputs self configure as either high or low side
drives.
Drain Connections of Output1-4 (DRN1-4)

These pins are connected to the drains of the n-channel MOSFET transistors.
Source Connections of Output1-4 (SRC1-4)

These pins are connected to the sources of the n-channel MOSFET transistors. Output 5-6
These two self-configuring outputs can be used to drive either high or low side loads. In addition to
be controlled by the SPI BUS these outputs can also be enabled and disabled via IN5 and IN6 inputs.
IN5 and IN6 inputs are logically ORed with the SPI commands to allow either the IN5-6 inputs or the
SPI commands to activate these outputs. The use of IN5-6 for PWM control on these outputs should
only be done with non-inductive loads. Integrated current source pull-ups and pull-downs are em-
ployed to correctly latch "open load" fault data. Both of these current sources are needed to detect
an open since these outputs self configure as either high or low side drives
Drain connections of Output5-6 (DRN5-6)

These pins are connected to the drains of the n-channel MOSFET transistors.
Source connections of Output5-6 (SRC5-6)

These pins are connected to the sources of the n-channel MOSFET transistors. Output7-8
These two outputs (DRN7-8) are dedicated low side drives. Integrated current source pull down are
required to correctly latch "open load" fault data.
Main Power Input (VDD)

The VDD input is the primary power source of the L9848. This supply is used as the power source for all of its
9/18
L9848

logic circuitry and other miscellaneous functions. Notice that if the L9848 is interfaced to a processor operating
with a lower voltage (e.g. 3.0 VDC), the microprocessor inputs connected to the L9848 will swing from 0 to 5.0
VDC.
Discrete Inputs (IN5-6)

These inputs allow Output5-6 to be enabled via this external pin without the use of the SPI. A logic "1" on these
inputs enables the corresponding output no matter what the status of the SPI command register. A logic "0" on
these inputs disables the corresponding output if the SPI command register is not commanding this output on.
These pins can be left "open" if the outputs are controlled only via the SPI (internally pulled down). These inputs
are ideally suited for non-inductive loads that are pulse width modulated (PWMed). This allows PWM control
without the use of the SPI. The TTL level compatible input voltages allow proper operation with microprocessors
that are using 5.0V or 3.0V for their Vdd supply.
Serial Peripheral Interface (SPI)

A standard serial peripheral interface, consisting of Serial Clock (SCLK), Data Out (DO), Data In (DI), and Chip
Select (CS) is implemented to allow access to the internal registers of the L9848. All outputs are controlled via
the SPI.The input pins CS, SCLK, and DI have TTL level compatible input voltages allowing proper operation
from microprocessors that are using 5.0V or 3.0V for their VDD supply. The design of the L9848 allows a "daisy-
chaining" of multiple L9848's to further reduce the need for controller pins. Serial Data Output (DO)
This output pin is in a tri-state condition when CS is a logic "0" (LOW). When CS is a logic "1" (HIGH),
this pin always transmits 8bits of data from the fault register to the digital controller. After the first 8bits
data are transmitted the DO output then sequentially transmits the digital data that was just received
(8 SCLK cycles earlier) on the DI pin. The DO output continues to transmit the 8 SCLK delayed bit
data from the DI input until CS eventually transitions from a logic "1" to a logic "0". DO data changes
state 10 ns or later, after the falling edge of SCLK. By definition, the MSB (Table 3) is the first bit of
the byte transmitted on DO and the LSB is the last bit of the byte transmitted on DO, once CS tran-
sitions from a logic "0" to a logic "1". Serial Data Input (DI)
This input takes data from the digital controller while CS is HIGH. The L9848 accepts an 8bit data
stream to command the outputs ON or OFF. By definition, the MSB (Table 1) is the first bit of each
byte received on DI and the LSB is the last bit of each byte received on DI, once CS transitions from
a logic "0" to a logic "1". Chip Select (CS)
This is the chip select input pin. On the rising edge of CS, the DO pin switches from tri-state to active-
out mode. While CS is high, register data is shifted in and shifted out by the DI and DO pin, respec-
tively, on each subsequent SCLK. On the falling edge of CS, the DO pin switches back to tri-state
mode and the fault register will be "Cleared" if a valid DI byte was received.
A valid DI byte is defined as such:
1st A multiple of 8 bits was received
2nd SCLK was low when CS went low
3rd Current SPI cycle started when SCLK was low
The fault data is not cleared unless all of the 3 previous conditions have been met. A SCLK transition
must be seen before CS is interpreted as active. To allow sufficient time to reload the fault registers,
the CS pin must remain low for a minimum of 1μs prior to going high again, before it starts shifting
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