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L9822N
OCTAL SERIAL SOLENOID DRIVER
L9822NOCTAL SERIAL SOLENOID DRIVER EIGHT LOW RDSon DMOS OUTPUTS
(0.5Ω AT IO = 1A @ 25°C VCC = 5V± 5%). 8 BIT SERIAL INPUT DATA (SPI). 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR
OVERLOAD AND OPEN CIRCUIT CONDITIONS. OUTPUT SHORT CIRCUIT PROTECTION. CHIP ENABLE SELECT FUNCTION (active low). INTERNAL 35V CLAMPING FOR EACH OUT-
PUT. CASCADABLE WITH ANOTHER OCTAL
DRIVER. LOW QUIESCENT CURRENT (10mA MAX.). PACKAGE Power SO20
DESCRIPTIONThe L9822N is an octal low side solenoid driver
rea lized in Multipower-BCD technology particularly
suited for driving lamps, relays and solenoids in au-
BLOCK DIAGRAMtomotive environment. The DMOS outpts L9822N
has a very low power consumption.
Data is transmitted serially to the device using the
Serial Peripheral Interface (SPI) protocol.
The L9822N features the outputs status monitoring
function.
October 1997 1/9
PIN CONNECTIONS (top view)
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
L9822N2/9
VCC
Logic supply voltage - nominally 5V
GROUND
Device Ground. This ground applies for the logic cir-
cuits as well as the power output stages.
RESET
Asynchronous reset for the output stages, the paral-
lel latch and the shift register inside the L9822NSP.
This pin is active low and it must not be left floating.
A power on clear function may be implemented con-
necting this pin to VCC with an external resistor and
to ground with an external capacitor.
Chip Enable. Data is transferred from the shift regi-
sters to the outputs on the rising edge of this signal.
The falling edge of this signal sets the shift register
with the output voltage sense bits coming from the
output stages. The output driver for the SO pin is
enabled when this pin is low.
Serial Output. This pin is the serial output from the
shift register and it is tri-stated when CE is high. A
high for a data bit on this pin indicates that the par-
ticular output is high. A low on this pin for a data bit
indicates that the output is low.
Comparing the serial output bits with the previous
serial input bits the external microcontroller imple-
ments the diagnostic data supplied by the L9822.
Serial Input. This pin is the serial data input. A high
on this pin will program a particular output to be OFF,
while a low will turn it ON.
SCLK
Serial Clock. This pin clocks the shift register. New
SO data will appear on every rising edge of this pin
and new SI data will be latched on every SCLK’s fal-
ling edge into the shift register.
OUTPUTS 00-07
Power output pins. The input and output bits corres-
ponding to 07 are sent and received first via the SPI
bus and 00 is the last.
The outputs are provided with current limiting and
voltage sense functions for fault indication and pro-
tection. The nominal load current for these outputs
is 500mA. The outputs also have on board clamps
set at about 36V for recirculation of inductive load
current.
PIN DESCRIPTION
ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%. Tj = – 40 to 125°C ; unless otherwise speciifed)
L9822N3/9
ELECTRICAL CHARACTERISTICS (Continued)INPUT BUFFER (SI, CE, SCLK and RESET pins)
OUTPUT BUFFER (SO pin)
SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram)
L9822N4/9
The L9822N DMOS output is a low operating power
device featu-ring, eight 1Ω RDSON DMOS drivers
with transient protection circuits in output stages.
Each channel is independently controlled by an out-
put latch and a common RESET line which disables
all eight outputs. The driver has low saturation and
short circuit protection and can drive inductive and re-
sistive loads such as solenoids, lamps and relais.
Data is transmitted to the device serially using the Se-
rial Peripheral Interface (SPI) protocol. The circuit re-
ceives 8 bit serial data by means of the serial input
(SI) which is stored in an internal register to control
the output drivers. The serial output (SO) provides 8
bit of diagnostic data representing the voltage level
at the driver output. This allows the microprocessor
to diagnose the condition of the output drivers.
The output saturation voltage is monitored by a
comparator for an out of saturation condition and is
able to unlatch the particular driver through the fault
reset line. This circuit is also cascadable with ano-
ther octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
line is low.
Additionally the (SO) is placed in a tri-state mode
when the device is deselected. The negative edge
of the (CE) transfers the voltage level of the drivers
to the shift register and the positive edge of the (CE)
latches the new data from the shift register to the dri-
vers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLK positive transition while data bit present at SI
input is latched into the shift register on every SCLK
negative transition.
Internal Blocks DescriptionThe internal architecture of the device is based on
the three internal major blocks : the octal shift regi-
ster for talking to the SPI bus, the octal latch for hol-
ding control bits written into the device and the octal
load driver array.
Shift RegisterThe shift register has both serial and parallel inputs
and serial and parallel outputs. The serial input ac-
cepts data from the SPI bus and the serial output si-
multaneously sends data into the SPI bus. The
parallel outputs are latched into the parallel latch in-
side the L9822N at the end of a data transfer. The
parallel inputs jam diagnostic data into the shift re-
gister at the beginning of a data transfer cycle.
Parallel LatchThe parallel latch holds the input data from the shift
register. This data then actuates the output stages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
output stages. The entire latch may also be cleared
by the RESET signal.
Output StagesThe output stages provide an active low drive signal
suitable for 0.75A continuous loads. The outputs
have internal zeners set to 36 volts to clamp induc-
tive transients at turn-off. Each output also has a
voltage comparator observing the output node. If the
voltage exceeds 1.8V on an ON output pin, a fault
condition is assumed and the latch driving this par-
ticular stage is reset, turning the output OFF to pro-
tect it. The timing of this action is described below.
These comparators also provide diagnostic feed-
back data to the shift register. Additionally, the com-
parators contain an internal pulldown current which
will cause the cell to indicate a low output voltage if
the output is programmed OFF and the output pin
is open circuited.
TIMING DATA TRANSFER
Figure #2 shows the overall timing diagram from a
byte transfer to and from the L9822NSP using the
SPI bus.
CE High to Low TransitionThe action begins when the Chip Enable (CE) pin is
pulled low. The tri-state Serial Output (SO) pin driver
will be enabled entire time that CE is low. At the fal-
ling edge of the CE pin, the diagnostic data from the
voltage comparators in the output stages will be lat-
ched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shift register. If the output is low, a logic zero will be
loaded there. The most significant bit (07) should be
presented at the Serial Input (SI) pin. A zero at this
pin will program an output ON, while a one will pro-
gram the output OFF.
SCLK TransitionsThe Serial Clock (SCLK) pin should then be pulled
high. At this point the diagnostic bit from the most si-
gnificant output (07) will appear at the SO pin. A high
here indicates that the 07 pin is higher than 1.8V.
The SCLK pin should then be toggled low then high.
New SO data will appear following every rising edge
of SCLK and new SI data will be latched into the
L9822N shift register on the falling edges. An unli-
mited amount of data may be shifted through the de-
vice shift register (into the SI pin and out the SO pin),
allowing the other SPI devices to be cascaded in a
daisy chain with the L9822N.
FUNCTIONAL DESCRIPTION
L9822N5/9
CE Low to High TransitionOnce the last data bit has been shifted into the
L9822NSP, the CE pin should be pulled high.
At the rising edge of CE the shift register data is lat-
ched into the parallel latch and the output stages will
be actuated by the new data. An internal 160μs de-
lay timer will also be started at this rising edge (see
tUD). During the 160μs period, the outputs will be
protected only by the analog current limiting circuits
since the resetting of the parallel latches by faults
conditions will be inhibited during this period. This al-
lows the part to overcome any high inrush currents
that may flow immediately after turn on. Once the
delay period has elapsed, the output voltages are
sensed by the comparators and any output with vol-
tages higher than 1.8V are latched OFF. It should be
noted that the SCLK pin should be low at both tran-
sitions of the CE pin to avoid any false clocking of
the shift register. The SCLK input is gated by the CE
pin, so that the SCLK pin is ignored whenever the
CE pin is high.
FAULT CONDITIONS CHECK
Checking for fault conditions may be done in the fol-
lowing way. Clock in a new control byte. Wait 160
microseconds or so to allow the outputs to settle.
Clock in the same control byte and observe the diag-
nostic data that comes out of the device. The diag-
nostic bits should be identical to the bits that were
first clocked in. Any differences would point to a fault
on that output. If the output was programmed ON by
clocking in a zero, and a one came back as the dia-
gnostic bit for that output, the output pin was still high
and a short circuit or overload condition exists. If the
output was programmed OFF by clocking in a one,
and a zero came back as the diagnostic bit for that
output, nothing had pulled the output pin high and it
must be floating, so an open circuit condition exists
for that output.
Figure 1 : Byte Timing with Asynchronous Reset.
L9822N6/9
