L9822E ,OCTAL SERIAL SOLENOID DRIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Logic Supply – 0.7 7 VCCV Output Voltage – ..
L9822EPD ,OCTAL SERIAL SOLENOID DRIVERL9822E®OCTAL SERIAL SOLENOID DRIVER. EIGHT LOW R DMOS OUTPUTS DSonMULTIPOWER BCD TECHNOLOGY(0.5Ω AT ..
L9822EPD013TR ,OCTAL SERIAL SOLENOID DRIVERELECTRICAL CHARACTERISTICS (Continued)Symbol Parameter Test Conditions Min. Typ. Max. UnitINPUT BUF ..
L9822EPD013TR ,OCTAL SERIAL SOLENOID DRIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV DC Logic Supply – 0.7 7 VCCV Output Voltage – ..
L9822N ,OCTAL SERIAL SOLENOID DRIVERELECTRICAL CHARACTERISTICS (Continued)Symbol Parameter Test Conditions Min. Typ. Max. UnitINPUT BUF ..
L9823 ,OCTAL LOW-SIDE DRIVER FOR BULB, RESISTIVE AND INDUCTIVE LOADS WITH SERIAL INPUT CONTROL, OUTPUT PROTECTION AND DIAGNOSTICBLOCK DIAGRAMV16 DDSFPDOUT0-15 OL0+ 24VDG=IOLCSBGateQ010Q0ControlQ1+Q2 I 0SCB -Q3Over-Q4OT0 Tempera ..
LC74763 ,On-Screen Display LSIElectrical Characteristics at Ta = –30 to +70°C, with V = V = 5 V unless otherwise specifiedDD1 DD2 ..
LC74772V ,Camcorder On-Screen Display LSIAbsolute Maximum RatingsParameter Symbol Conditions Ratings UnitSupply voltage V V V – 0.3 to V + 7 ..
LC74775 ,On-Screen Display Controller ICPin AssignmentNo. 5919-2/35LC74775, 74775MPin FunctionsPin no. Pin Function Notes1 V 1 Ground Groun ..
LC74780 ,On-screen Video Display Controllers for VCRsBlock DiagramPam—wimh Fixel-holghl p119. pixal Fhshlngmumer cuunlor mums: caumav| ' 1_ * ‘ Decode! ..
LC74780 ,On-screen Video Display Controllers for VCRsFeaturesI Complete text and graphics video overlay circuitryI 128-charaeter internal character gene ..
LC74780M ,On-Screen Video Display Controllers for VCRsBlock DiagramNo.4490–2/14LC74780, 74780MPin FunctionsNe umberNn am Descriptio1V GroundSS12N XIInter ..
L9822E-L9822EPD
OCTAL SERIAL SOLENOID DRIVER
L982 2EOCTAL SERIAL SOLENOID DRIVER EIGHT LOW RDSon DMOS OUTPUTS
(0.5Ω AT IO = 1A @ 25°C VCC = 5V± 5%). 8 BIT SERIAL INPUT DATA (SPI). 8 BIT SERIAL DIAGNOSTIC OUTPUT FOR
OVERLOAD AND OPEN CIRCUIT CONDITIONS. OUTPUT SHORT CIRCUIT PROTECTION. CHIP ENABLE SELECT FUNCTION (active low). INTERNAL 36V CLAMPING FOR EACH OUT-
PUT. CASCADABLE WITH ANOTHER OCTAL
DRIVER. LOW QUIESCENT CURRENT (10mA MAX.). PACKAGE MULTIWATT15 AND PowerSO20
DESCRIPTIONThe L9822E is an octal low side solenoid driver
rea lized in Multipower-BCD technology particularly
suited for driving lamps, relays and solenoids in
BLOCK DIAGRAMautomotive environment. The DMOS outpts
L9822E has a very low power consumption.
Data is transmitted serially to the device using the
Serial Peripheral Interface (SPI) protocol.
The L9822E features the outputs status monitoring
function.
January 2002 1/10
PIN CONNECTIONS (top view)
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
L9822E2/10
VCC
Logic supply voltage - nominally 5V
GROUND
Device Ground. This ground applies for the logic cir-
cuits as well as the power output stages.
RESET
Asynchronous reset for the output stages, the par-
allel latch and the shift register inside the
L9822ESP. This pin is active low and it must not be
left floating. A power on clear function may be im-
plemented connecting this pin to VCC with an exter-
nal resistor and to ground with an external capacitor.
Chip Enable. Data is transferred from the shift reg-
isters to the outputs on the rising edge of this signal.
The falling edge of this signal sets the shift register
with the output voltage sense bits coming from the
output stages. The output driver for the SO pin is en-
abled when this pin is low.
Serial Output. This pin is the serial output from the
shift register and it is tri-stated when CE is high. A
high for a data bit on this pin indicates that the par-
ticular output is high. A low on this pin for a data bit
indicates that the output is low.
Comparing the serial output bits with the previous
serial input bits the external microcontroller imple-
ments the diagnostic data supplied by the L9822.
Serial Input. This pin is the serial data input. A high
on this pin will program a particular output to be OFF,
while a low will turn it ON.
SCLK
Serial Clock. This pin clocks the shift register. New
SO data will appear on every rising edge of this pin
and new SI data will be latched on every SCLK’s fall-
ing edge into the shift register.
OUTPUTS 00-07
Power output pins. The input and output bits corres-
ponding to 07 are sent and received first via the SPI
bus and 00 is the last. The outputs are provided with
current limiting and voltage sense functions for fault
indication and protection. The nominal load current
for these outputs is 500mA, but the current limiting
is set to a minimum of 1.05A. The outputs also have
on board clamps set at about 36V for recirculation
of inductive load current.
PIN DESCRIPTION
ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%. Tj = – 40 to 125°C ; unless otherwise speciifed)
L9822E3/10
ELECTRICAL CHARACTERISTICS (Continued)INPUT BUFFER (SI, CE, SCLK and RESET pins)
OUTPUT BUFFER (SO pin)
SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram)
L9822E4/10
The L9822ESP DMOS output is a low operating
power device featu-ring, eight 1Ω RDSON DMOS
drivers with transient protection circuits in output
stages. Each channel is independently controlled by
an output latch and a common RESET line which dis-
ables all eight outputs. The driver has low saturation
and short circuit protection and can drive inductive
and resistive loads such as solenoids, lamps and re-
lais. Data is transmitted to the device serially using
the Serial Peripheral Interface (SPI) protocol. The cir-
cuit receives 8 bit serial data by means of the serial
input (SI) which is stored in an internal register to con-
trol the output drivers. The serial output (SO) pro-
vides 8 bit of diagnostic data representing the voltage
level at the driver output. This allows the micropro-
cessor to diagnose the condition of the output drivers.
The output saturation voltage is monitored by a
comparator for an out of saturation condition and is
able to unlatch the particular driver through the fault
reset line. This circuit is also cascadable with an-
other octal driver in order to jam 8 bit multiple data.
The device is selected when the chip enable (CE)
line is low.
Additionally the (SO) is placed in a tri-state mode
when the device is deselected. The negative edge
of the (CE) transfers the voltage level of the drivers
to the shift register and the positive edge of the (CE)
latches the new data from the shift register to the
drivers. When CE is Low, data bit contained into the
shift register is transferred to SO output at every
SCLK positive transition while data bit present at SI
input is latched into the shift register on every SCLK
negative transition.
Internal Blocks DescriptionThe internal architecture of the device is based on
the three internal major blocks : the octal shift reg-
ister for talking to the SPI bus, the octal latch for hold-
ing control bits written into the device and the octal
load driver array.
Shift RegisterThe shift register has both serial and parallel inputs
and serial and parallel outputs. The serial input ac-
cepts data from the SPI bus and the serial output
simultaneously sends data into the SPI bus. The
parallel outputs are latched into the parallel latch in-
side the L9822ESP at the end of a data transfer. The
parallel inputs jam diagnostic data into the shift reg-
ister at the beginning of a data transfer cycle.
Parallel LatchThe parallel latch holds the input data from the shift
register. This data then actuates the output stages.
Individual registers in the latch may be cleared by
fault conditions in order to protect the overloaded
output stages. The entire latch may also be cleared
by the RESET signal.
Output StagesThe output stages provide an active low drive signal
suitable for 0.75A continuous loads. Each output
has a current limit circuit which limits the maximum
output current to at least 1.05A to allow for high in-
rush currents. Additionally, the outputs have internal
zeners set to 36 volts to clamp inductive transients
at turn-off. Each output also has a voltage compara-
tor observing the output node. If the voltage exceeds
1.8V on an ON output pin, a fault condition is as-
sumed and the latch driving this particular stage is
reset, turning the output OFF to protect it. The timing
of this action is described below. These compara-
tors also provide diagnostic feedback data to the
shift register. Additionally, the comparators contain
an internal pulldown current which will cause the cell
to indicate a low output voltage if the output is pro-
grammed OFF and the output pin is open circuited.
TIMING DATA TRANSFER
Figure #2 shows the overall timing diagram from a
byte transfer to and from the L9822ESP using the
SPI bus.
CE High to Low TransitionThe action begins when the Chip Enable (CE) pin is
pulled low. The tri-state Serial Output (SO) pin driver
will be enabled entire time that CE is low. At the fall-
ing edge of the CE pin, the diagnostic data from the
voltage comparators in the output stages will be
latched into the shift register. If a particular output is
high, a logic one will be jammed into that bit in the
shift register. If the output is low, a logic zero will be
loaded there. The most significant bit (07) should be
presented at the Serial Input (SI) pin. A zero at this
pin will program an output ON, while a one will pro-
gram the output OFF.
SCLK TransitionsThe Serial Clock (SCLK) pin should then be pulled
high. At this point the diagnostic bit from the most
significant output (07) will appear at the SO pin. A
high here indicates that the 07 pin is higher than
1.8V. The SCLK pin should then be toggled low then
high. New SO data will appear following every rising
edge of SCLK and new SI data will be latched into
the L9822ESP shift register on the falling edges. An
unlimited amount of data may be shifted through the
device shift register (into the SI pin and out the SO
FUNCTIONAL DESCRIPTION
L9822E5/10
