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L9777-L9777A-L9777A13TR-L9777B-L9777B13TR
Low power voltage regulator
February 2014 DocID13496 Rev 4 1/25
L9777Low power voltage regulator
Datasheet - production data
Features Operating DC supply voltage range 5.6 V to V Low current consumption (110 μA typ @ Iout = 0) High precision output voltage (2 %) Low dropout voltage VDD tracking regulator switchable on/off by
VDD_EN pin Reset circuit sensing the output voltage down
to 1 V. Double reset function Adjustable reset threshold External capacitor to set NMI/ reset power up
delay and watchdog frequency Over temperature protection Wide temperature range (TJ = -40 °C to 150 °C) Short circuit proof Suitable for use in automotive electronics
DescriptionThe L9777 is a monolithic integrated low drop
regulator which can supply up to 200 mA,
available in the PowerSSO-12 package.
It is designed to supply microprocessor systems
under severe conditions of automotive
applications and therefore equipped with
additional protection functions against over load,
short circuit and over temperature.
Of course the L9777 can also be used in other
applications where a regulated voltage is
required.
Table 1. Device summary
Order code Package PackingL9777A PowerSSO-12 Tray
L9777B PowerSSO-12 Tray
L9777B13TR PowerSSO-12 Tape and reel
L9777C PowerSSO-12 Tray
L9777C13TR PowerSSO-12 Tape and reel
Contents L97772/25 DocID13496 Rev 4
Contents Block diagrams and pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Block diagram (option A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Option B features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Option C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 NMI and RESET driver delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4 RESET adjustable threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VDD regulated voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VDD_LOW (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186.1 Option A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Option B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Option C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DocID13496 Rev 4 3/25
L9777 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Electrical and thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 5. Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
List of figures L9777
4/25 DocID13496 Rev 4
List of figures
Figure 1. Block diagram (option A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 2. Package pin configuration (options A and B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 3. Block diagram (option B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. Block diagram (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 5. Package pin configuration (option C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 6. VCC versus output current IVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 7. Filter time between VCC and NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8. Reset time diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 9. Filter time between NMI and RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Figure 10. RESET and NMI drivers fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 11. Resistor divider to adjust the under voltage threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 12. Watchdog timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 13. VDD_LOW filter time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 14. PowerSSO-12 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . .23
DocID13496 Rev 4 5/25
L9777 Block diagrams and pins configuration Block diagrams and pins configuration
1.1 Block diagram (option A)
Figure 1. Block diagram (option A)
1.2 Option B features VDD can sustain short to 40 V regardless of VI battery voltage Current capability of VDD scaled down to 50 mA with dropout of 1.5 V (Max.) In default condition, VDD and WD functions are disabled using 2 pull down current on
VDD_EN and WD_EN pin Standby current consumption reduced to 100 μA (Typ.)
Figure 2. Package pin configuration (options A and B)
Block diagrams and pins configuration L9777 DocID13496 Rev 4
Figure 3. Block diagram (option B)
Figure 4. Block diagram (option C)
DocID13496 Rev 4 7/25
L9777 Block diagrams and pins configuration
1.3 Option C features VDD can sustain short to 40 V regardless of VI battery voltage Current capability of VDD scaled down to 50 mA with dropout of 1.5V (Max.) In default condition, VDD and WD functions are disabled using 2 pull down current on
VDD_EN and WD_EN pin Double reset function removed and pin RESET used to detect undervoltage condition
on VDD regulated voltage (VDD_LOW pin)
Figure 5. Package pin configuration (option C)
Table 2. Pin description
Pin# I/O Name Function O RESET/VDD_LOW
OPTION A & B: RESET output.
This pin is set low if NMI output goes low for adjustable filter time
OPTION C: VDD_LOW output
This pin is set low when undervoltage on VDD is detected O NMI
Non maskable Interrupt Output
This pin is set low when low voltage on VCC is detected or
frequency of WD signal is too low. D
NMI/RESET power up delay.
External cap on this pin sets the time response of the VCC low
voltage detector and the time response of the watchdog monitor. I VDD_EN
VDD control.
OPTION A: If this pin is low VDD output voltage is not available
(connect this pin to VCC or left floating to switch on VDD output
voltage)
OPTION B & C: If this pin is low or left floating VDD output
voltage is not available (connect this pin to VCC to switch on
VDD regulator) WD
Watchdog input.
If the frequency at this input pin is too low, the NMI output is
activated low
Block diagrams and pins configuration L9777
8/25 DocID13496 Rev 4 I WD_EN
Watchdog function enable/disable
OPTION A: If this pin is low the watchdog function is disabled, if
connected to VCC or left floating the watchdog function is
enabled.
OPTION B & C: If this pin is low or floating, the watchdog
function is disabled, if connected to VCC the watchdog function is
enabled. VI Input voltage
Block to GND with a capacitor of value at least 100 nF I TIMING
OPTION A & B: RESET filter time
External cap on this pin sets the delay time between NMI and
RESET output
OPTION C: not used and should be left floating or shorted to
ground. O VCC Voltage regulator output
External cap CVCC 220 nF is needed to stabilize the regulator O VDD
VDD
Output regulated voltage switched on/off by VDD_EN pin.
External cap CVDD=100 nF is needed to stabilize the regulator GND Ground I RADJ
VCC under voltage Threshold Adjustment
By connecting this pin to an external resistor divider vs. VCC, is
possible to set the VCC under voltage threshold.
If this pin is connected to GND the under voltage threshold is set
by internal circuit.
Table 2. Pin description (continued)
Pin# I/O Name Function
DocID13496 Rev 4 9/25
L9777 Absolute maximum ratings Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
Input voltage VI
VVI Voltage -0.3 40 V
IVI Current Internal limited
VCC
VVCC Voltage -0.3 5.5 V
IVCC Current Internal limited
NMI
VNMI Voltage -0.3 VCC+0.3 V
INMI Current Internal limited Voltage -0.3 VCC+0.3 V
Current Internal limited
RADJ
VRADJ Voltage -0.3 VCC+0.3 V
IRADJ Current Internal limited
VWD Voltage -0.3 VCC+0.3 V
IWD Current Internal limited
WD_EN
VWD_EN Voltage -0.3 VCC+0.3 V
IWD_EN Current Internal limited
VDD_EN
VVDD_EN Voltage -0.3 VCC+0.3 V
IVDD_EN Current Internal limited
RESET
VRESET Voltage -0.3 VCC+0.3 V
IRESET Current Internal limited
Absolute maximum ratings L9777
10/25 DocID13496 Rev 4
Timing
VI + 0.3 (Opt. A)
40V (Opt. B)
Not connected (Opt. C)
VTIMING Voltage -0.3 - V
ITIMING Current Internal limited
VDD
VVDD Voltage -0.3
VI + 0.3 (Opt. A)
40V (Opt. B)
40V (Opt. C)
IVDD Current Internal limited
Temperature Junction temperature -40 150 °C
ESD voltage level
VESD HBM-MIL STD 883C -1.5 1.5 kV
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Min. Max. Unit
DocID13496 Rev 4 11/25
L9777 Functional description
3 Functional description
3.1 Voltage regulator
This device supply an always active 5 V regulated voltage on pin VCC with a current
capability up to 200 mA. VCC voltage has an accuracy of 2% over a wide supply voltage
(VI = 5.6 V to 31 V) and temperature range (TJ = -40 °C to 150 °C).
A short circuit protection to GND is provided (see Figure 6).
By means of tracking regulator, it is available a second output regulated voltage on pin VDD
with a current capability up to 50 mA. This regulated output is switchable on/off by external
pin VDD_EN.
Figure 6. VCC versus output current IVCC
3.2 Reset
The reset circuit monitors the output voltage VCC. In case of internal reset threshold, if the
output voltage stays lower than VCCUN for a filter time TRR, then NMI goes low.
This filter time depends on the distance between the VCC output and the under voltage
reset threshold (VCCUN): this solution increases the noise immunity of the voltage regulator
be-cause the filter time between the reset event and the falling of NMI output changes
according to the depth of spike on output voltage (see following picture).
A minimum filter time of 1 μs (TRR1) is guaranteed if VCC goes down to 2.5 V and
VS > 5.6 V.
Figure 7. Filter time between VCC and NMI
Otherwise, in case of external reset threshold fixed by means of external resistor divider on
pin RADJ, there is only a constant filter time (TRRADJ) of 1 μs min value.
Functional description L9777
12/25 DocID13496 Rev 4
In both cases, if the output voltage VCC becomes lower than 2.0V (typ) than NMI may go
immediately low without any delay. The NMI low signal is guaranteed for an output voltage
VCC greater than 1V.
When VCC returns over VCCUN threshold NMI goes high with a filter time TRD. This time is
obtained by 127 period of an oscillator with an additional initial time. The oscillator period is
given by:
TOSC VDU VDRL– CD
IRC ----------------------------------------------------------- VDU VDRL– CD
IRD -----------------------------------------------------------+=
where:
ICR = 20 μA (typ) is a current internally generated,
IDR = 20 μA (typ) is a current internally generated,
VDU = 1.24 V and VDRL = 0.62 V are two typical internal thresholds,
CD is the external capacitance on pin D.
TRD is given by:
TRD (s) = T0 + 127 x TOSC = 0.62*10-3 + 7.874* 106 * CD (typ)
Where T0 is the initial ramp between 0 V and VDU as in Figure 8.
Figure 8. Reset time diagram
If NMI output goes to 0 V for filter time TRESDF (which is fixed by external cap on TIMING
pin) also the RESET signal goes to 0 V. RESET low signal is guaranteed for VCC > 1 V.
Figure 9. Filter time between NMI and RESET
DocID13496 Rev 4 13/25
L9777 Functional description
3.3 NMI and RESET driver delay
NMI and RESET pins are driven by bipolar transistor with a maximum current capability
internally limited of value respectively INMIL and IRESL.
For this reason, when the drivers are activated, the capacitors present on pin NMI or
RESET are discharged with constant current. The waveform on output pin is a voltage ramp
with a slope linearly dependent on external capacitance.
The fall time needed by drivers to discharge external capacitor can be calculated in first
approximation using this expression.fall Cext lim
-----------------------------=
Where V is the voltage difference between 90% and 10% of total voltage swing of the
transition, Cext is the total pin capacitance and Ilim is the current limitation of the driver
(IRESL and INMIL).
Figure 10. RESET and NMI drivers fall time
