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L9659
Octal squib driver ASIC for safety application
September 2013 Doc ID 022048 Rev 2 1/51
L9659Octal squib driver ASIC for safety application
Features 8 deployment drivers with SPI selectable firing
current and times Capability to deploy the squib with 1.2 A
(min)/2 ms, 1.75 A (min)/1.0 ms and 1.75 A
(min)/0.65 ms between VRES of 7 V to 37 V Capability to deploy the squib with 1.5 A
(min)/2 ms between VRES of 7 V to 25 V Firing capability to deploy all channels
simultaneously Independently controlled high-side and low-
side MOS for diagnosis Analog output available for resistance measurement Squib short to ground, short to battery and
MOS diagnostic available on SPI register Capability to deploy the squib the low side
MOS is shorted to ground 4 fire enable inputs 5.5 MHz SPI interface Low voltage internal reset 2 kV ESD capability on all pins Package: LQFP64 Technology: ST proprietary BCD5 (0.65 µm) RoHS compliant
DescriptionThe L9659 is intended to deploy up to 8 squibs.
Squib drivers are sized to deploy 1.2 A minimum
for 2 ms, 1.75 A minimum for 1 ms and 1.75 A
minimum for 0.65 ms during load dump along with
1.5 A minimum for 2 ms for VRES voltages less
than 25 V.
Full diagnostic capabilities of the squib interface
are provided.
Table 1. Device summary
Contents L96592/51 Doc ID 022048 Rev 2
Contents Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . 10
2.3 Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4.2 Electrical characteristics - Squib deployment drivers and diagnostics . . 12
2.4.3 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 General functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.1 Power on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.2 RESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2.3 Reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.4 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 VRESx capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.6 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.7 Ground connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1 SPI pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Squib drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.1 Firing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.2 Firing current measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.3 Fire enable (FEN) function description . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.4 Squib diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.5 SPI register definition for squib functions . . . . . . . . . . . . . . . . . . . . . . . . 31
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
L9659 List of tables
Doc ID 022048 Rev 2 3/51
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Absolute maximum degraded operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. General - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics . . . . . . . . . . . . . 12
Table 8. SPI timing - DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. Features that are accessed/controlled for the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. SPI MOSI/MISO response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. How faults shall be interpreted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Diagnostic Mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. Diagnostic mode 3 VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. MISO responses to various events. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. Command description summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Configuration mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Configuration mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. Deployment mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 19. Deployment mode 2 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 20. Diagnostic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. Diagnostic mode LS FET selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 22. Diagnostic mode HS FET selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. Diagnostic mode HSS selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 24. Diagnostic mode VRESx selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 25. Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. MOSI diagnostic mode 1 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. DEPLOY_STATUSx flag and the DEPLOY_SUCCESSx flag conditions. . . . . . . . . . . . . . 44
Table 28. MOSI monitor mode 2 Bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 29. Current measurement channel selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 30. MOSI monitor mode 3 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 31. MOSI monitor mode 4 bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 32. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of figures L9659
4/51 Doc ID 022048 Rev 2
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. MOS settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. MISO loading for disable time measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. POR timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Deployment drivers diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 8. Driver activation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. Squib diagnostics block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. LQFP64 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
L9659 Block diagram and pin description
Doc ID 022048 Rev 2 5/51 Block diagram and pin description
1.1 Block diagram
Figure 1. Block diagram
1.2 Pin description
Table 2. Pin description
Block diagram and pin description L9659
6/51 Doc ID 022048 Rev 2
Table 2. Pin description (continued)
L9659 Block diagram and pin description
Doc ID 022048 Rev 2 7/51
Table 2. Pin description (continued)
Block diagram and pin description L9659
8/51 Doc ID 022048 Rev 2
1.3 Application schematic
Figure 2. Application schematic
L9659 Electrical specifications
Doc ID 022048 Rev 2 9/51
2 Electrical specifications
2.1 Absolute maximum ratings
The following maximum ratings are continuous absolute ratings; exceeding any one of these
values may cause permanent damage to the integrated circuit.
Table 3. Absolute maximum ratings Exceeding a VDD of 5.1V during a deployment may cause damage To allow for deployment the maximum steady state junction temperature cannot exceed 130°C. Under the operating ratings
defined in section 2.3 the steady state junction temperature will not exceed 130°C.
Electrical specifications L9659
10/51 Doc ID 022048 Rev 2
2.2 Absolute maximum degraded operating ratings
Under the following deviations to the ratings indicated in Section 2.3 the L9659 performance
will be degraded and not meet the electrical characteristics outlined in Section 2.4. At
minimum the SPI and diagnostics will function but not meet specified electrical parameters.
Note: The above is provided for informational purposes only and will result in degraded operation.
Under the above conditions the SPI will be functional as well as diagnostics, though the
electrical performance may not conform to the parameters outlined in Section 2.4. Firing
requirements as indicated in Section 2.4 may not be met with the conditions above.
2.3 Operating ratings
Comments:
VSDIAG supply will provide power for squib resistance and HSS diagnostics
VDD will be used for all internal functions as well as short to battery/ground and high squib
resistance diagnostics.
Table 4. Absolute maximum degraded operating ratings
Table 5. Operating ratings
L9659 Electrical specifications
Doc ID 022048 Rev 2 11/51
2.4 Electrical characteristics
2.4.1 General
4.9 V VDD 5.1 V; 7 V VRESX 37 V; 7 V VSDIAG 37 V; FEN1 = FEN2 = FEN3 =
FEN4 = VDD; R_REF = 10 k, ±1 %, 100 PPM; -40 °C TA +95 °C; unless other specified.
Table 6. General - DC electrical characteristics
Electrical specifications L9659
12/51 Doc ID 022048 Rev 2
2.4.2 Electrical characteristics - Squib deployment drivers and diagnostics
4.9 V VDD 5. 1V; 7 V VRESX 37 V; 7 V VSDIAG 37 V; FEN1 = FEN2 = FEN3 = FEN4
= VDD; R_REF = 10 k, ±1%, 100 PPM; -40 °C TA +95 °C; C_VRES0_1 68nF;
C_VRES2_3 68nFC_VRES4_5 68nF; C_VRES6_7 68nF; unless other specified.
Table 6. General - DC electrical characteristics (continued)
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics
L9659 Electrical specifications
Doc ID 022048 Rev 2 13/51
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
Electrical specifications L9659
14/51 Doc ID 022048 Rev 2
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
L9659 Electrical specifications
Doc ID 022048 Rev 2 15/51
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
Electrical specifications L9659 Doc ID 022048 Rev 2
Figure 3. MOS settling time and turn-on time 2
Table 7. Squib deployment drivers and diagnostics - DC electrical characteristics (continued)
L9659 Electrical specifications
Doc ID 022048 Rev 2 17/51
2.4.3 SPI timing
All SPI timing is performed with a 150 pF load on MISO unless otherwise noted
4.9V VDD 5.1V; 7V VRESX 37V; 7V VSDIAG 37V; FEN1 = FEN2 = FEN3 = FEN4 =
VDD; R_REF = 10K, ±1%, 100PPM; -40°C TA +95°C; C_VRES0_1 68nF;
C_VRES2_3 68nF; C_VRES4_5 68nF; C_VRES6_7 68nF; unless other specified.
.Table 8. SPI timing - DC electrical characteristics Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance
on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable
time, and minimum capacitance on MISO is the worst case for output hold time.
Electrical specifications L9659
18/51 Doc ID 022048 Rev 2
Figure 4. SPI timing diagram
Figure 5. MISO loading for disable time measurement
L9659 Functional description
Doc ID 022048 Rev 2 19/51
3 Functional description
3.1 Overview
The L9659 is an integrated circuit to be used in air bag systems. Its main functions include
deployment of air bags. The L9659 supports 8 deployment loops.
3.2 General functions
3.2.1 Power on reset (POR)
The ASIC has a power on reset (POR) circuit, which monitors VDD voltage. When VDD
voltage falls below VRST1 for longer than or equal to tPOR, all outputs are disabled and all
internal registers are reset to their default condition. A second reset level, VRST2, also
monitors VDD but uses no filter time and will disable all outputs and all internal registers are
reset to their default condition when VDD falls below the reset threshold.
Figure 6. POR timing
3.2.2 RESETB
The RESETB pin is active low. The effects of RESETB are similar to those of a POR event,
except during a deployment. When a deployment is in-progress, the L9659 will ignore the
RESETB signal.
However, it will shut itself down as soon as it detects a POR condition. When the
deployment is completed and RESETB signal is asserted, the L9659 disables its outputs
and reset its internal registers to their default states.
A de-glitch timer is provided for the RESETB pin. The timer protects this pin against
spurious glitches. The L9659 neglects RESETB signal if it is asserted for shorter than
tGLITCH. RESETB has an internal pull-up in case of an open circuit.
Functional description L9659
20/51 Doc ID 022048 Rev 2
3.2.3 Reference resistor
IREF pin shall be connected to VDD supply through a resistor, RIREF . When the L9659
detects the resistor on IREF pin is larger than RIREF_H or smaller than RIREF_L, it goes
into a reset condition. All outputs are disabled and all internal registers are reset to their
default conditions.
3.2.4 Loss of ground
GND
When the GND pin is disconnected from PC-board ground, the L9659 goes in reset
condition. All outputs are disabled and all internal registers are reset to their default
conditions.
GND0-GND7
A loss of power-ground (GND0 – GND7) pin/s disables the respective low side driver/s on
SQLx. However, the high side driver of the respective channel will still be able to be turned
on. Thus under the scenario where the low side is shorted to ground the L9659 will be able
to provide the programmed firing current for the specified time.
An open GNDx connection on any channel has no affect on the other channels. An open
GNDx condition will be detected using the low side MOS diagnostics.
AGND
The AGND pin is a reference for AOUT pin. When AGND loses its connection, the voltage
on AOUT pin is pulledup to VDD voltage and L9659 goes in reset condition. All outputs are
disabled and all internal register are reset to their default conditions.
3.2.5 VRESx capacitance o ensure all diagnostics function properly a typical capacitor of equal to or greater than
68nF is required close to the firing supply pins. Thus minimum of 4 capacitors are required
with one placed close to the VRES0 and VRES1 pins and a second capacitor will be close
to the VRES2 and VRES3 pins and a third capacitor will be close to the VRES4 and VRES5
pins and a forth capacitor will be close to the VRES6 and VRES7 pins.
3.2.6 Supply voltages
The primary current sources for the different functions of the ASIC are as follows: VRESx - Firing currents along with HSS and HS FET diagnostic currents VSDIAG - Squib resistance and HSS diagnostics VDD will be used for all internal functions as well as short to battery/ground and high
squib resistance diagnostics.
3.2.7 Ground connections
GND pin (6) is not connected internally to other ground pins (AGND or power ground
GNDx). A ground plane is needed to directly connect the GND pin. This ground plane needs
to be isolated from the high current ground for the squib drivers to prevent voltage shifts.
AGND pin should be connected to ground plane too to minimize drop versus ground
reference of ADC that capture AOUT voltage.
L9659 Functional description
Doc ID 022048 Rev 2 21/51
3.3 Serial peripheral interface (SPI)
The L9659 contains one serial peripheral interfaces for control of the squib functions. The
following table shows features that are accessed/controlled by the SPI.
.
The software reset accessed over SPI will reset squib functions. The L9659 has a counter to
verify the number of clocks in SCLK. If the number of clocks in SCLK is not equal to 16
clocks while CS_D is asserted, it ignores the SPI message and sends a SPI fault response.
L9659 computes SPI error length flag through counting the number ofSCLK rising edges
occurring when CS_D is active. If the first SCLK rising edge occurs when CS_D is inactive
and the falling edge occurs when CS_D is low, it is considered as valid edge.
MOSI commands contain several bits not used, all those bits must be 0. Commands are not
recognized valid if one or more not used bits are not 0.
3.3.1 SPI pin descriptions
Chip select (CS_D)
Chip-select inputs select the L9659 for serial transfers. CS_D can be asserted at any given
time and are active low. When chip-select is asserted, the respective MISO pin is released
from tri-state mode, and all status information is latched into the SPI shift register. While
chip-select is asserted, register data is shifted into MOSI pin and shifted out of MISO pin on
each subsequent SCLK. When chip-select is negated, MISO pin is tri-stated. To allow
sufficient time to reload the registers; chip-select pin shall remain negated for at least tCSN.
The chip-select inputs have current sinks which pull these pins to the negated state when
there is an open circuit condition. These pins have TTL level compatible input voltages
allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
Serial clock (SCLK)
SCLK input is the clock signal input for synchronization of serial data transfer. This pin has
TTL level compatible input voltages allowing proper operation with microprocessors using a
3.3 to 5.0 volt supply. When chip select is asserted, both the SPI master and L9659 will latch
input data on the rising edge of SCLK. The L9659 shifts data out on the falling edge of
SCLK.
Serial data output (MISO)
MISO output pins shall be in one tri-state condition when chip select is negated. When chip
select is asserted, the MSB is the first bit of the word/byte transmitted on MISO and the LSB
is the last bit of the word/byte transmitted. This pin supplies a rail to rail output, so if
interfaced to a microprocessor that is using a lower VDD supply, the appropriate
microprocessor input pin shall not sink more than IOH(min) and shall not clamp the MISO
output voltage to less than VOH(min) while MISO pin is in a logic “1” state. When connecting
to a micro using a lower supply, such as 3.3V, a resistor divider shall be used with high
enough impedance to prevent excess current flow.
Table 9. Features that are accessed/controlled for the SPI
Functional description L9659
22/51 Doc ID 022048 Rev 2
Serial data input (MOSI)
MOSI inputs take data from the master processor while chip select is asserted. The MSB
shall be the first bit of each word/byte received on MOSI and the LSB shall be the last bit of
each word/byte received.
This pin has TTL level compatible input voltages allowing proper operation with
microprocessors using a 3.3 to 5.0 volt supply.
3.4 Squib drivers
3.4.1 Firing
The on-chip deployment drivers are designed to deliver 1.2A (min) for 2ms (min) and 1.75A
(min) for 1ms (min)and 1.75A (min) for 0.65ms (min) with VRESx voltages between 7V and
37V. In addition the L9659 can provide 1.5A minimum for 2ms for VRESx voltages between
7V and 25V . The firing condition is selectable via the SPI. At the end of a deployment, a
deploy success flag is asserted and can be read using the appropriate SPI command. Each
VRESx and GNDx connection is used to accommodate 8 loops that can be deployed
simultaneously.
Upon receiving a valid deployment condition, the respective SQHx and SQLx drivers are
turned on. The only other activation of the SQHx and SQLx drivers is momentarily during a
MOS diagnostic. Otherwise, SQHx and SQLx are inactive under any normal, fault, or
transient conditions. Upon a successful deployment of the respective SQHx and SQLx
drivers, a deploy command success flag is asserted via SPI. Refer to Figure 8. for the valid
conditions and the deploy success flag timing.
The L9659 is protected against inadvertent turn on of the firing drivers unless the
appropriate conditions are present. Non-typical conditions will not cause driver activation.
This includes the case where VRESx and/or VSDIAG pins are connected to a supply up to
40V and VDD is between 0V and VDD min. Under these conditions the L9659 will ensure
that driver activation will not occur. No flow of current shall be allowed through the SQHx
and SQLx pins.
L9659 Functional description
Doc ID 022048 Rev 2 23/51
Figure 7. Deployment drivers diagram
Driver activation
The firing of a squib driver requires the appropriate FEN function to be active and two
separate sixteen bit writes be made over the SPI. The FEN function is defined as the result
of the FENx pin OR’d with the internal FENx latch. The FENx pin going high initiates the
FEN function. With the FEN 1 function being active and the appropriate Arm and Fire
commands sent then Squib_0 & 1 drivers would be activated. With the FEN 2 function being
active and the appropriate Arm and Fire commands sent then Squib_2 & 3 drivers would be
activated. With the FEN 3 function being active and the appropriate Arm and Fire
commands sent then Squib_4 & 5 drivers would be activated. With the FEN 4 function being
active and the appropriate Arm and Fire commands sent then Squib_6 & 7 drivers would be
activated.
The first write is to ARM the drivers in preparation of receiving the fire command. The Arm
command will stop on all channels any diagnostics that are active. Any combination of
squibs can be armed. The second write is a FIRE command that must directly follow the
Arm command and will activate the desired driver pairs assuming the FEN function is valid.
If there is a parity mismatch the data bits will be ignored and the squib drivers will not have
their status changed, and the two write sequence must then be started again. If there is a
mismatch in channels selected then only those channels selected in both the Arm and Fire
commands will be activated.
Functional description L9659
24/51 Doc ID 022048 Rev 2
During the first write, when the drivers are armed, all diagnostic functions are cleared. The
FIRE command must follow the ARM command along with the FEN function active for driver
activation. If a command is between the ARM and FIRE command then the sequence must
be restarted. An error response will be received for the Fire command if the ARM/FIRE
sequence is not followed.
The ARM/FIRE commands and FEN function are independent from each other. The L9659
will begin the tDEPLOY timer once a valid ARM/FIRE sequence has been received. If a valid
ARM/FIRE command has been sent and the FEN function is inactive then the drivers will not
be activated but the tDEPLOY timer will start. If the FEN function becomes active before
tDEPLOY has expired then the drivers will become active for the full tDEPLOY time. If the FEN
does not become active before tDEPLOY has expired then the sequence would need to be
restarted. A diagram illustrating this is shown in Figure 8.
Figure 8. Driver activation timing diagram
Only the channels selected in the ARM and, directly following, the FIRE command will be
able to be activated.
By reading the appropriate registers a status of the deployment is provided. If a valid
Arm/Fire sequence has been provided the status flag will become active. This flag will
remain active for as long as the TDEPLOY timer is counting. Depending on the state of the
FEN function the DEPLOY_STATUS flag will be active a minimum of TDEPLOY and a
maximum of 2 x TDEPLOY . If driver activation did occur (both a valid Arm/Fire sequence and
the appropriate FEN function active within the appropriate time) then the
DEPLOY_SUCCESS flag will be active following the completion of the driver activation
period. This flag will be active until cleared by software. If a valid Arm/Fire sequence did
occur but the FEN function was never activated within the TDEPLOY time then the
DEPLOY_SUCCESS flag will remain ‘0’.
Once the Deploy Success Flag is set, it will inhibit the subsequent deployment command
until a SPI command to clear this deployment success flag is received. Bits D7 through bit
D0 are used to clear/keep the deploy success flag. When these bits are set to ‘1,’ the flag
L9659 Functional description
Doc ID 022048 Rev 2 25/51
can be cleared. Otherwise, the state of these flags is not affected. The Success flag must be
cleared to allow re-activation of the drivers.
During driver activation the respective high side (SQHx) and low side (SQLx) drivers will turn
on for tDEPLOY.
L9659 driver activation will not occur or, if firing is in process, will terminate under the
following conditions: Power On Reset (POR) IREF resistance is larger than RIREF_H or smaller than RIREF_L Loss of ground condition on GND pin
The following conditions are ignored when driver activation is in-progress: RESETB Valid soft reset sequences SPI commands except as noted below. Response for ignored commands will be
0xD009 FEN function
The following table shows the response when sending SPI commands during deployment.
Note 1: SPI MISO sent in the next SPI transmission.
The L9659 can only deploy a channel when the FEN function is active. Once the drivers are
active the L9659 will keep the drivers on for the required duration regardless of the FEN
state. Once complete a status bit will be set to indicate firing is complete.
3.4.2 Firing current measurement
All channels have a 7 bit current measurement register that is used to measure the amount
of time the current is above IMEAS during firing. The maximum measurement for each
channel is 3.175ms nominal based on a bit weight of 25µs. The current measurement
register will not increment outside the deployment time. The current measurement will begin
incrementing once the current has exceeded 95% of the nominal target value. The count will
continue to increment from the stored value until either a clear command has been issued
for that channel or all ‘1’s are present in the corresponding channel measurement register. If
all ‘1’s are present for a channel’s measurement register and another firing sequence has
been issued the register will remain all ‘1’s. Only if a clear command has been issued will
that particular register be reset to all ‘0’s. All other channels shall keep the stored
measurement count. During firing the current measurement register cannot be cleared.
After a clear command has been issued for a channel then the channel is ready to count if
Table 10. SPI MOSI/MISO response
Functional description L9659
26/51 Doc ID 022048 Rev 2
the current exceeds the specified level. After a POR or software reset the L9659 will reset all
8 measurement registers to all ‘0’s.
A “real-time” current measurement status of all the channels is available. If a current limit
status request is sent then the L9659 will report in the next SPI transfer whether the current
is above or below IMEAS for each of the channels. The current status results can be read at
any time and will correctly report whether current is flowing. The content of the internal
current status register is captured on the falling edge of chip select during the SPI response.
The internal status register is updated at a nominal sample time of 25µs and is independent
of SPI transfers.
For this circuit there is continuously being performed compensation of the comparator to
remove offset errors, which is independent from SPI commands. The compensation is being
performed every 12.8µs based on the internal clock.
3.4.3 Fire enable (FEN) function description
The Fire Enable (FEN) function is the result of the FENx input OR’d with the internal FEN
latch. If the FEN latch is not enabled and the FENx pin is low then activation of the FET
drivers are disabled except as indicated during the MOS test. All internal diagnostic
functions, and results, will be available through the serial interface. This pin must be pulled
high to initiate the FEN latch function (if programmed) and enable firing of the FET drivers.
There are four FEN function blocks FEN Function 1 is FEN1 input OR’d with FEN1 latch timer and used for enabling
channels 0 & 1 FEN Function 2 is FEN1 input OR’d with FEN2 latch timer and used for enabling
channels 2 & 3 FEN Function 3 is FEN1 input OR'd with FEN3 latch timer and used for enabling
channels 4 & 5 FEN Function 4 is FEN1 input OR'd with FEN4 latch timer and used for enabling
channels 6 & 7
The FEN function will be considered active when the pin is active (‘1’ or high) for more than
12 microseconds. T olerance range for the filter used is 12 to 16 µsecs.
When the FENx input is active, ‘1’, the FEN function will be active. When the FENx input
state transitions from ‘1’ to ‘0’, the programmable latching function will hold the FEN
function active until the timeout of the FEN timer. The programmable latch and hold
function will be capable of delays of 0ms, 128 ms, 256 ms, and 512 ms. There are 4
independent timers with the timer for FEN1 associated with channels 0 & 1, timer for FEN2
associated with channels 2 & 3, timer for FEN3 associated with channels 4 & 5, timer for
FEN4 associated with channels 6 & 7. The timer is reset to the programmed time when
the FENx pin transitions from ‘0’ to ‘1’. The programmable counter delay will be set
through a SPI command.
