L9658 ,Quad squib driver and dual sensor interface ASIC for safety applicationFunctional description . . . . . . 184.1 Overview . 184.2 Power on reset (POR) . . ..
L9659 ,Octal squib driver ASIC for safety applicationFeatures that are accessed/controlled for the SPI . . . . . . . 21Table 10. SPI MOSI/MISO respon ..
L9660 ,Quad squib driver ASIC for safety applicationFeatures that are accessed/controlled for the SPI . . . . . . . 20Table 10. SPI MOSI/MISO respon ..
L9669 ,FAULT TOLERANT CAN TRANSCEIVERBlock DiagramKL30(+12V)+5VVoltageRegulatorVS INH VCC5Vint 14 1 1075k7 Wake-upWAKEControlCANHVCCDriv ..
L9686 ,AUTOMOTIVE DIRECTION INDICATORELECTRICAL CHARACTERISTICS (– 20°C < Tamb <, 100°C, 8V < VS < 18V unless otherwise speci-fied.)Symb ..
L9700 ,HEX PRECISION LIMITERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage 20 VCCI Input Current per Chann ..
LC74402 ,PIP ControllersOrdering number: EN X4872No.y.44872PreliminaryOverviewThe LC74401E. LC74402, and LC74402E are memor ..
LC74402E ,PIP ControllersFeatures. Horizontal resolution: 600 TV lines"l. Three D/A converters (for the Y, R-Y, and B-Y sign ..
LC7441 ,Picture-in-picture Controller for TVs and VCRsPin AssignmentsRAOUT YAOUTNC BAOUTVREF AVSSems en AVDDKLPFO' so CLAMPDAKLPFI 59 ESOLPFI se KOUTOLPF ..
LC74411N ,PIP ControllerFeatures• Horizontal resolution: 450 pixels*• Single-chip implementation of the three circuits requ ..
LC74411NE ,PIP ControllerOrdering number : EN*5519ACMOS LSILC74411N, LC74411NEPIP ControllerPreliminaryOverview Package Dime ..
LC7441N ,Picture-in-picture Controller for TVs and VCRsFeatures include stilllactive dis-play, white/color frame, F1xedlvariable (screen)positioning, and ..
L9658
Quad squib driver and dual sensor interface ASIC for safety application
September 2013 Doc ID 14219 Rev 3 1/64
L9658 Octal squib driver and quad sensor interface
ASIC for safety application
Features 8 deployment drivers sized to deliver 1.2 A
(min) for 2 ms (min) and 1.75 A (min) for 1 ms
(min) Independently controlled high-side and low-
side MOS for diagnosis Analog output available for resistance Squib short to ground, short to battery and
MOS diagnostic available on SPI register Capability to deploy the squib with 1.2 A (min)
or 1.75 A under 35 V load-dump condition and
the low side MOS is shorted to ground Capability to deploy the squib with 1.2 A (min)
at 6.9 V VRES and 1.75 A at 12 V VRES Interface with 4 satellite sensors Programmable independent current trip points
for each satellite channel Support Manchester protocol for satellite
sensors Supports for variable bit rate detection Independent current limit and fault timer
shutdown protection for each satellite output Short to ground and short to battery detection
and reporting for each satellite channel 5.5 MHz SPI interface Satellite message error detection Hall effect sensor support on satellite channels
3 and 4. Low voltage internal reset 2 kV ESD capability on all pins Package: 64 leads LQFP Technology: ST proprietary BCD5s (0.57 µm)
DescriptionL9658 is intended to deploy up to 8 squibs and to
interface up to 4 satellites. 2 satellite interfaces
can be used to interface Hall sensors.
Squib drivers are sized to deploy 1.2 A minimum
for 2 ms minimum during load dump and 1.75 A
minimum for 1ms minimum during load dump.
Diagnostic of squib driver and squib resistance
measurement is controlled by micro controller.
Satellite interfaces support Manchester decoder
with variable bit rate.
Table 1. Device summary
Contents L96582/64 Doc ID 14219 Rev 3
Contents Block diagram and application schematic . . . . . . . . . . . . . . . . . . . . . . . 71.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Power on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 RESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Deployment and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8.1 Chip select (CS_A, CS_D, CS_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8.2 Serial clock (SCLK, SCLK_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8.3 Serial data output (MISO, MISO_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.8.4 Serial data input (MOSI, MOSI_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9.1 Arming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.10 DEPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10.1 Deployment driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.10.2 Continuity diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.10.3 Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L9658 ContentsDoc ID 14219 Rev 3 3/64
4.10.4 Short to ground and open circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.10.5 Resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10.6 MOS diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10.7 Low side MOS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.10.8 High side MOS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.10.9 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.11 Deployment driver SPI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.1 Deployment driver MOSI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.2 Deployment driver register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.11.3 Deployment driver command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.11.4 Deployment driver diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.11.5 Example of short between loops diagnostic . . . . . . . . . . . . . . . . . . . . . 38
4.11.6 Deployment driver monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.11.7 Deployment driver MISO bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.11.8 Deployment driver register mode response . . . . . . . . . . . . . . . . . . . . . . 41
4.12 MISO register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.12.1 Deployment driver command mode response . . . . . . . . . . . . . . . . . . . . 43
4.12.2 Deployment driver diagnostic mode response . . . . . . . . . . . . . . . . . . . . 44
4.12.3 Deployment driver status response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.12.4 Deployment driver SPI fault response . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13 Arming SPI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13.1 Arming MOSI_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13.2 ARM[01..67] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.13.3 ARM[01..67]* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.13.4 Arming MISO_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.13.5 ARM[01..67] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.14 Satellite sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.14.1 Current sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14.2 Manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.14.3 Communication protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.14.4 "A" protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.14.5 "B" variable length protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.14.6 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.14.7 Satellite continuity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.14.8 (IFx/Vx) hall effect support mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.14.9 (IFx/Vx) raw data out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.14.10 Message waiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Contents L96584/64 Doc ID 14219 Rev 3
4.14.11 Satellite serial data input (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.14.12 Satellite MOSI bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.14.13 Satellite module configuration register (CH1 only) . . . . . . . . . . . . . . . . 53
4.14.14 Channel configuration registers (CCR1, CCR2, CCR3, CCR4) . . . . . . . 54
4.14.15 SPI MISO Bits layout for configuration report . . . . . . . . . . . . . . . . . . . . 58
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
L9658 List of tables
Doc ID 14219 Rev 3 5/64
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Maximum operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. DC specification general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. DC Specification: deployment drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Satellite interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 9. AC specification: deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC specifications: satellite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. SPI transmission during a deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. Deployment driver SPI response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14. MOSI bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. MOSI mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. MOSI register mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Pulse stretch timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 18. MOSI command mode message definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. MOSI diagnostic mode message definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Channel selection decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 21. MOSI monitor mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 22. MISO bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 23. MISO mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 24. MISO register mode response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 25. MISO register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26. MISO command mode response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27. MISO diagnostic mode response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 28. MISO status response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 29. MISO SPI fault response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 30. Arming MOSI_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 31. Arming MISO_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 32. Satellite MOSI bits layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 33. MOSI satellite interface registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. Master configuration register definition (CH1 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. Channel configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 36. Current ranges supported are given in following table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 37. Satellite/decoder control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 38. "B" protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 39. Bit time selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 40. Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 41. SPI mode selects reply for satellite channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 42. Satellite MISO bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 43. SPI MISO bits layout when reporting FIFO data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 44. MISO Manchester message data definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 45. Status bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 46. Satellites fault codes definition supporting “A” protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 47. Satellites fault codes definition supporting “B” protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 48. Hall effect fault codes definition (CH3 and CH4) only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 49. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
List of figures L9658
6/64 Doc ID 14219 Rev 3
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. MOS settling time and turn-on time 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4. MOS settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. SPI timing measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Arming daisy-chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Arming SPI transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Deployment drivers diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Deployment sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Deployment flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Deployment driver diagnostic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 14. Continuity diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Resistance measurement flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Low side diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. High side driver diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Satellite interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 19. Manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 20. Manchester decoding using satellite protocol as an example . . . . . . . . . . . . . . . . . . . . . . 49
Figure 21. "A" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 22. "B" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 23. LQFP64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
L9658 Block diagram and application schematic Block diagram and application schematic
1.1 Block diagram
Figure 1. Block diagram
1.2 Application schematic
Figure 2. Application schematic
Pin description L9658
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2 Pin description
Table 2. Pin function
L9658 Pin description
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2.1 Thermal data
Table 2. Pin function (continued)
Table 3. Thermal Data
Electrical specification L9658
10/64 Doc ID 14219 Rev 3
3 Electrical specification
3.1 Maximum ratings
The device may not operate properly if maximum operating condition is exceeded.
3.2 Absolute maximum ratings
Caution: Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
Table 4. Maximum operating conditions
Table 5. Absolute maximum ratings
L9658 Electrical specification
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3.3 Electrical characteristics
3.3.1 DC characteristics
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 6. DC specification general VRST shall have a POR de-glitch timer. VRST L shall have no timer.
Electrical specification L9658
12/64 Doc ID 14219 Rev 3
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 7. DC Specification: deployment drivers Not applicable during a diagnostic. Test conditions for load resistance measurements
L9658 Electrical specification
Doc ID 14219 Rev 3 13/64
VDD = 4.9 to 5.1V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 8. Satellite interface DC specifications
Electrical specification L9658
14/64 Doc ID 14219 Rev 3
3.3.2 AC characteristics
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 9. AC specification: deployment drivers Application Information; Test is not performed at high voltage. Design Information Only
L9658 Electrical specification 15/64
Figure 3. MOS settling time and turn-on time 1
Figure 4. MOS settling time and turn-on time 2
Electrical specification L9658
16/64 Doc ID 14219 Rev 3
VDD = 4.9 to 5.1 V; V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 10. AC specifications: satellite
L9658 Electrical specification
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VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40° C to +95 °C
All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.
Figure 5. SPI timing diagram
Figure 6. SPI timing measurement
Table 11. SPI timing Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on
the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time,
and minimum capacitance on MISO is the worst case for output hold time.
Functional description L9658
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4 Functional description
4.1 Overview
L9658 is an integrated circuit to be used in air bag systems. Its main functions include
deployment of air bags, switched-power sources to satellite sensors, diagnostics of SDM
(Sensing Deployment Module) and arming inputs. L9658 supports 8 deployment loops, 4
satellite-sensor interfaces, and SPI arming inputs.
4.2 Power on reset (POR)
L9658 has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage
falls below VRST for longer than or equal to tPOR, all outputs are disabled and all internal
registers are reset to their default condition.
When VDD falls below VRST_L, all outputs are disabled and all internal registers are reset to
their default condition. No delay filter shall be used along with VRST_L threshold.
If VDD voltage falls below VRST for less than tPOR, operation shall not be interrupted.
When VDD rises above VRST, the outputs are enabled. Before VDD reaches VRST, and during
tPOR, none of the outputs turn on.
4.3 RESETB
RESETB pin is active low. The effects of RESETB are similar to those of a POR event,
except during a deployment. When L9658 has a deployment in-progress, it ignores
RESETB signal.
However, it shall shut itself down as soon as it detects a POR condition. When the
deployment is completed and RESETB signal is asserted, the device disables its outputs
and reset its internal registers to their default states.
A de-glitch timer is provided to RESETB pin. The timer protects this pin against spurious
glitches. UT48 neglects RESETB signal if it is asserted for shorter than tGLITCH. RESETB
has an internal pull-up in case of an open circuit. This pin has a de-glitch timer
4.4 MSG
MSG pin is used to reflect FIFO status. Its polarity can be configured and also the strategy
of activation.
Polling mode: Message pin shall be active as soon as one of the 4 FIFO will be not empty
and it will be inactive when all 4 FIFO will be empty. A microcontroller can periodically
monitor the status of line to understand there are data received from satellite. Interrupt
mode: Message pin shall be active as soon one of the 4 FIFO will be not empty and it will be
inactive when a spi communication on CS_S interface starts. At the end of the SPI
communication it shall be active if one of the 4 FIFO will be not empty. Otherwise shall be
kept inactive. A microcontroller can wait until an edge is present on the line and manage the
data available in the FIFO.
L9658 Functional description
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4.5 IREF
IREF pin shall be connected to VDD supply through a resistor, RIREF. When the device
detects the resistor on IREF pin is larger than RIREF_H or smaller than RIREF_L, it goes in
reset condition. All outputs are disabled and all internal registers are reset to their default
conditions.
4.6 Loss of ground
When GND pin is disconnected from PC-board ground, L9658 goes in reset condition. All
outputs are disabled and all internal registers are reset to their default conditions. A loss of
power-ground (GND0 – GND7) pin/s disables the respective channel/s. In other words, the
channel that loses its power ground connection will not be able to deploy. The rest of the
device is not affected by a loss of power-ground condition.
AOUT_GND pin is a reference for AOUT pin. When AOUT_GND loses its connection the reset
as well.
4.7 Deployment and reset
The following conditions reset and terminate deployments: Power On Reset (POR) IREF resistance is larger than RIREF_H or smaller than RIREF_L Loss of ground condition on GND pin
The following conditions are ignored when it has a deployment in-progress: RESETB Valid soft reset sequences
4.8 Serial peripheral interface (SPI)
The device contains a serial peripheral interface consisting of Serial Clock (SCLK,
SCLK_A), Serial Data Out (MISO, MISO_A), Serial Data In (MOSI, MOSI_A), and two Chip
Selects (CS_A, CS_D and CS_S). This device is configured as an SPI slave. The idle state
of the communication, Serial Clock (SCLK, SCLK_A) should be low state.
Functional description L9658
20/64 Doc ID 14219 Rev 3
Figure 7. SPI block diagram
L9658 has a counter to verify the number of clocks in SCLK and SCLK_A. If the number of
clocks in SCLK is not equal to 16 clocks while CS_D is asserted, it ignores the SPI message
and send a SPI fault response. If the number of clocks in SCLK is not equal to 64 clocks
while CS_S is asserted, it ignores the entire SPI message and push the Bad SPI Bit Count
fault code into the FIFO. If the number of clocks in SCLK_A is not a multiple of 8, it ignores
the command in the arming shift register. Otherwise, the device latch-in the command.
Figure 8. Arming daisy-chain configuration
Arming SPI interface is based on 8-bit data transfer. The device is capable to receive a
multiple of 8-bit commands. The first byte of data coming out of MISO_A will be the arming
status bits. The subsequent bits will be the arming command bits received through MOSI_A
pin. Refer to below figure for an example of arming SPI transmission. This is an example of
arming SPI transmission based on the daisy-chain configuration.
In case of daisy chain connection for Arming SPI, device works as following:
All devices IC_1, IC_2, IC_3 shifted out data on the falling edge of SCLK_A for the first 8 bits
and shifted out data on the rising edge of SCLK_A for the bits after 8bits. therefore µP , IC_3,
IC_2 shall strobe 24bits on rising edge of SCLK_A, the first 8 bits are produced (by IC_3,
IC_2, IC_1 respectively) on the falling edge of SCLK_A. the remaining 16 bits are shifted out
on the rising edge.
L9658 Functional description
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Figure 9. Arming SPI transmission
4.8.1 Chip select (CS_A, CS_D, CS_S)
Chip-select inputs select L9658 for serial transfers. CS_A is independent to CS_D and
CS_S.
CS_A can be asserted regardless of CS_D and CS_S. However, either CS_D or CS_S can
be asserted at any given time. If both CS_D and CS_S inputs are selected simultaneously,
the device ignores MOSI command. When chip-select is asserted, the respective
MISO/MISO_A pin is released from tri-state mode, and all status information is latched in
the SPI shift register. While chip-select is asserted, register data is shifted into
MOSI/MOSI_A pin and shifted out of MISO/MISO_A pin on each subsequent
SCLK/SCLK_A. When chip-select is negated, MISO/MISO_A pin is tri-stated. To allow
sufficient time to reload the registers; chip-select pin shall remain negated for at least tCSN.
Chip-select is also immune to spurious pulses of 50 ns or shorter (MISO/MISO_A may
come out of tri-state, but no status bits is cleared and no control bits is changed).
Chip-select inputs have current sinks on the pins, which pull these pins to the negated state
when an open circuit condition occur. These pins have TTL level compatible input voltages
allowing proper operation with microprocessors using a 3.3 to 5.0 V supply.
4.8.2 Serial clock (SCLK, SCLK_A)
SCLK/SCLK_A input is the clock signal input for synchronization of serial data transfer. This
pin has TTL level compatible input voltages allowing proper operation with microprocessors
using a 3.3 to 5.0 V supply. When chip select is asserted, both the SPI master and this
device shall latch input data on the rising edge of SCLK/SCLK_A. L9658 shift data out on
the falling edge of SCLK/SCLK_A. The SCLK/SCLK_A must be taken in idle state (LOW)
when the CS_A,CS_D,CS_S are in idle state (LOW). (a)
4.8.3 Serial data output (MISO, MISO_A)
MISO/MISO_A output pin shall be in a tri-state condition when chip select is negated. When
chip select is asserted, the MSB is the first bit of the word/byte transmitted on
MISO/MISO_A and the LSB is the last bit of the word/byte transmitted. This pin supplies a
rail to rail output, so if interfaced to a microprocessor that is using a lower VDD supply, the
appropriate microprocessor input pin shall not sink more than IOH (min) and shall not clamp
the MISO/MISO_A output voltage to less than VOH (min) while MISO/MISO_A pin is in a
logic “1” state. Only in daisy chain, it is needed to guarantee on SCLK_A a clock skew of 3ns maximum between any devices.
Functional description L9658
22/64 Doc ID 14219 Rev 3
4.8.4 Serial data input (MOSI, MOSI_A)
MOSI/MOSI_A input takes data from the master processor while chip select is asserted.
The MSB shall be the first bit of each word/byte received on MOSI/MOSI_A and the LSB
shall be the last bit of each word/byte received. This pin has TTL level compatible input
voltages allowing proper operation with microprocessors using a 3.3 to 5.0 V supply.
4.9 Deployment drivers
The on-chip deployment drivers are designed to deliver 1.2 A (min) at 6.9 V VRES.
Deployment current is be 1.2 A (min) for 2 ms (min). The high side driver survives
deployment with 1.47 A, 35 V at VRES and SQL is shorted to ground for 2.5ms. Minimum
load resistance is 1.7. At the end of a deployment, a deploy success flag is asserted via SPI.
Each VRES and GND connection are used to accommodate 8 loops that can be deployed
simultaneously.
Upon receiving a valid deployment condition, the respective SQH and SQL drivers are
turned on. SQH and SQL drivers are also turned on momentarily during a MOS diagnostic.
Otherwise, SQH and SQL are inactive under any normal, fault, or transient conditions. Upon
a successful deployment of the respective SQH and SQL drivers, a deploy command
success flag is asserted via SPI. Refer to "deployment sequence" figure for the valid
condition and the deploy success flagh timing.
Figure 10. Deployment drivers diagram
L9658 Functional description
Doc ID 14219 Rev 3 23/64
The following power-up conditions is considered as normal operations. VRES input can be
connected to either a power supply output or an ignition voltage. VDD is connected to 5 V
output of power supply. When VRES is connected to the power supply, VDD voltage will
reach its regulation voltage before VRES voltage is stabilized. In this condition, the device
has the control o f its internal logic and that prevent an inadvertent turn-on of the drivers.
When VRES is connected to the ignition, VRES voltage will be stabilized before VDD
reaches its regulation voltage. In this condition, all drivers are inactive. A pull-down on the
gates of high side drivers (SQH) is provided to prevent these drivers from momentarily
turning-on. Any loop driver fault conditions do not turn on the SQH and SQL drivers. Only a
valid deployment condition can turn on the respective SQH and SQL drivers. Refer to
section for valid deployment conditions.
4.9.1 Arming interface
The arming interface is used as a fail-safe to prevent inadvertent airbag deployment. Along
with deployment command, these signals provide redundancy. Pulse stretch timer is
provided for each channel/loop. Either ARM signal or deployment command shall start the
pulse stretch timer.
Arming interface has a dedicated 8-bit SPI interface.
When CS_A is negated, L9658 latch ARM signal from the shift register and start the pulse
stretch timer for the respective channel/s. The device can deploy a channel, ONLY when
DEPEN is asserted and any of the following conditions are satisfied: the respective deployment command is sent during a valid pulse stretch timer,
which initiated by ARM signal the respective SPI ARM command is sent during a valid pulse stretch timer, which
initiate by deployment command
During a deployment, the device turn on the respective high side (SQH) and low side (SQL)
drivers for duration of tDEPLOY. When a deployment is initiated, it cant be terminated, except
during a reset event.
Figure 11. Deployment sequence
When a deployment-enable command is sent through SPI, the pulse stretcher shall be
initiated immediately following the falling edge of CS_D. When another deployment-enable
Functional description L9658 Doc ID 14219 Rev 3
command is sent before the timer for the previous command expired, the timer is refreshed.
Sending a deployment-disable command will terminate the pulse stretch timer operation.
ONLY a timer operation started by a deployment-enable command can be terminated. A
deployment-en/disable command does not affect the timer operation started by arming
signal.
When an arming-enable command is sent through SPI, the pulse stretcher is initiated
immediately following the falling edge of CS_A. When another arming-enable command is
sent before the timer for the previous command expired, the timer is refreshed. Sending an
arming disable command terminate the pulse stretch timer operation. ONLY a timer
operation started by an arming-enable command can be terminated. An arming-en/disable
command does not affect the timer operation started by a valid deployment command.
Figure 12. Deployment flow chart MOSI Register Mode: ignored. Next MISO: SPI fault response
MOSI Command Mode: execute for channels NOT in deployment, NO effect to deploying
channel. Next MISO: Command mode response
MOSI Diagnostic Mode: ignored. Next MISO: SPI fault response
MOSI Monitor Mode: execute for all channels. Next MISO: Status response
L9658 Functional description
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During the deployment, L9658 turn on the respective high (SQH) and low side (SQL) drivers
for tDEPLOY. Once deployment is initiated it can not be terminated. When a channel is in
deployment, this particular channel shall only act upon certain SPI messages. These SPI
messages and their responses are summarized in below table. The rest of the channels
shall resume their operations and respond to specific SPI commands.
During a deployment, the device ignores arming commands. and does not refresh or
terminate the pulse stretch timer when it receives an arming command.
4.10 DEPEN
DEPEN is a deployment enable input, which is an active high input. When this pin is
asserted, L9658 is able to turn on its high and low side drivers upon receiving a valid
deployment command or a MOS diagnostic request. DEPEN can not interrupt a deployment
that is already in-progress.
When DEPEN is negated, it inhibits the low side and the high side MOS from turning on
(inhibit the deployment). When a MOS diagnostic is requested, the device executes the
diagnostic even without the ability to turn on the MOS. It set the proper SPI threshold bits.
SPI remains functional while this pin is pulled low.
When DEPEN is negated, SPI deploy command is prevented from initiating the pulse stretch
timer. Regardless of DEPEN, SPI deploy command status bits reports the state of SPI
deploy command bits sent in the previous SPI transfer. This feature is required so that the
processor can diagnose SPI deploy command bits with DEPEN negated.
Regardless of DEPEN, arming signal is able to initiate the pulse stretch timer. This feature
will be used for the processor to diagnose the arming signal.
When the pulse stretch timer has been running, changes in the state of DEPEN does not
affect the pulse stretch timer. The pulse stretch timer is not affected regardless of the pulse
stretch timer being started by an arming signal or a SPI deploy command.
A de-glitch timer is provided to DEPEN pin. The timer protects this pin against spurious
glitches. The device neglects DEPEN signal if it is asserted/negated for shorter than GLITCH.
Table 12. SPI transmission during a deployment SPI MISO sent in the next SPI transmission.
Functional description L9658
26/64 Doc ID 14219 Rev 3
4.10.1 Deployment driver diagnostic
L9658 is able to perform a short to battery, a short to ground, a resistance measurement
and a MOS diagnostics on its deployment drivers. A short to ground and an open circuit
conditions are distinguished using a resistance measurement. Here below is shown the
diagram of deployment driver diagnostic.
The diagnostic is performed when a valid SPI command is received. Each current sources
(ISRC and IBIAS) and current sinks (ISINK, IPD_SQH) are turn on or off by a SPI command.
IPD_SQH is turned on when IBIAS is turned on. This pull-down (IPD_SQH) is used to deplete
the charge left on the SQH and SQL capacitors. IPD is permanently connected to SQL. This
current sink pull-down SQL pin during an open circuit condition.
Diagnostic current source or sink and comparator or amplifier are independent. It is possible
to turn on or off the current source or sink on a specific channel, while monitoring the
comparator or amplifier on a different channel. This feature is used to run a short between
loop diagnostic.
Figure 13. Deployment driver diagnostic diagram
L9658 Functional description
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4.10.2 Continuity diagnostic
A continuity diagnostic includes a short to battery, a short to ground and an open circuit
diagnostics.
During a continuity diagnostic, IBIAS is switched on. On a normal loading condition, SQH
voltage is below SBTH threshold and SQL voltage will be above SGTH threshold.
Figure 14. Continuity diagnostic flow chart
4.10.3 Short to battery
A short to battery condition will be detected when the voltage on SQH is greater than SBTH
threshold voltage.
4.10.4 Short to ground and open circuit
A short to ground or an open circuit conditions are detected when the voltage on SQL is less
than SGTH threshold voltage. A resistance measurement is utilized to differentiate between
a short to ground or an open circuit conditions.
Functional description L9658
28/64 Doc ID 14219 Rev 3
4.10.5 Resistance measurement
During a resistance measurement, both ISRC and ISINK are switched on. An analog
voltage on AOUT pin is provided. AOUT pin is a 5 V analog pin, which will be connected to the
ADC input of a processor. This pin provides the resistance-measurement voltage, which
correspond to the voltage difference across SQH and SQL. According to the following
formula:
Vaout = VDD/10 + Rsquib · Isrc · 10
The accuracy in the range of Rsquib is classified as followings:
0 < Rsquib 3.5 ±95 mV
3.5 < Rsquib 10 ±5 %
A low pass filter (10 k + 330 pF) is recommended in order to cancel noise caused by
internal offset compensation.
Figure 15. Resistance measurement flow chart
4.10.6 MOS diagnostics
During diagnostic, IBIAS is connected to SQH pin. In a normal condition, SQH voltage is
below SBTH and SQL voltage will be higher than SGTH. Prior to turning on the MOS, the
processor is expected to check for a short to battery and a short to ground fault. This step is
intended to prevent a large amount of current flowing through the MOS. Also, this step is
intended to precondition SQH and SQL pins prior to diagnostics. DEPEN pin is asserted in
order to turn on the low or high side driver. If DEPEN is negated during diagnostic, the MOS
is not turned on and a fail MOS diagnostic is expected.
4.10.7 Low side MOS diagnostic
When L9658 receives a SPI command to initiate the low side driver diagnostic, verification
of following conditions are done before turning on the low side driver:
–VSQL greater than SGTH threshold voltage
–VSQH less than SBTH threshold voltage
If both conditions above are satisfied, execution of low side driver diagnostic is performed.
Otherwise, the low side MOS diagnostic request is ignored and both bit D13 and bit D7 in
SPI diagnostic mode response are set. Upon detection of the following conditions, the
L9658 Functional description
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device turns the low side driver off and terminate the diagnostic within the specified time,
tPROP_DLY.
–VSQL less than SGTH threshold voltage
–(VSQHx – VSQLx) greater than VI_TH
–VSQH greater than SBTH threshold voltage
The state of each comparator above is reported through SPI. When the device detects one
of the above conditions, the respective SPI status bit to indicate the condition is set. Any of
the above conditions will be considered as normal in a low side MOS diagnostic.
The low side driver is turned off when tTIMEOUT is expired. A fault detection filter, tFLT_DLY, is
provided to protect against short-transients on SQH and SQL pins.
Figure 16. Low side diagnostic flow chart
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30/64 Doc ID 14219 Rev 3
4.10.8 High side MOS diagnostic
When L9658 receives a SPI command to initiate the high side MOS diagnostic, the following
conditions are verified before turning on the high side MOS:
–VSQL greater than SGTH threshold voltage
–VSQH less than SBTH threshold voltage
If both conditions above are satisfied, the high side MOS diagnostic is executed. Otherwise,
it ignored and both bit D13 and bit D7 in SPI diagnostic are set.
Upon detection of the following conditions, the high side driver is turned off and the
diagnostic, within the specified time, tPROP_DLY, is terminated
–VSQH greater than SBTH threshold voltage
–(VSQHx – VSQLx) greater than VI_TH
–VSQL less than SGTH threshold voltage
The state of each comparator above is reported through SPI. When L9658 detects one of
the above conditions, it set the respective SPI status bit to indicate the condition. Any of the
above conditions will be considered as normal in a high side MOS diagnostic.
The high side driver is turned off when tTIMEOUT is expired. A fault detection filter, tFLT_DLY, is
provided to protect against short-transients on SQH and SQL pins.
4.10.9 Loss of ground
When any of the power grounds (GND0 – 7) are lost, no deployment can occur to the
respective deployment channels. A loss of ground condition on one or several channels will
not affect the operation of the remaining channels.
When a loss of ground condition occurs, the source of the low side MOS will be floating. In
this case, no current will flow through the low side driver.
This condition will be detected as a fault by a low side MOS diagnostic. Also, the resistance
measurement result will be on the low end of the resistance range.
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Figure 17. High side driver diagnostic flow chart
Functional description L9658
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4.11 Deployment driver SPI bit definition
The SPI provides access to read/write to the registers internal to the device, which
responses to various deployment driver commands summarized in table below.
L9658 response to the previous command is sent in the next valid CS_D.
4.11.1 Deployment driver MOSI bit definition
MOSI mode bits are defined as shown in below table.
Table 13. Deployment driver SPI response
Table 14. MOSI bit layout
Table 15. MOSI mode bits definition
