L9654 ,Quad squib driver and dual sensor interface for safety applicationFunctional description . . . . . . 184.1 Overview . 184.2 Power on reset (POR) . . ..
L9658 ,Quad squib driver and dual sensor interface ASIC for safety applicationFunctional description . . . . . . 184.1 Overview . 184.2 Power on reset (POR) . . ..
L9659 ,Octal squib driver ASIC for safety applicationFeatures that are accessed/controlled for the SPI . . . . . . . 21Table 10. SPI MOSI/MISO respon ..
L9660 ,Quad squib driver ASIC for safety applicationFeatures that are accessed/controlled for the SPI . . . . . . . 20Table 10. SPI MOSI/MISO respon ..
L9669 ,FAULT TOLERANT CAN TRANSCEIVERBlock DiagramKL30(+12V)+5VVoltageRegulatorVS INH VCC5Vint 14 1 1075k7 Wake-upWAKEControlCANHVCCDriv ..
L9686 ,AUTOMOTIVE DIRECTION INDICATORELECTRICAL CHARACTERISTICS (– 20°C < Tamb <, 100°C, 8V < VS < 18V unless otherwise speci-fied.)Symb ..
LC74402 ,PIP ControllersOrdering number: EN X4872No.y.44872PreliminaryOverviewThe LC74401E. LC74402, and LC74402E are memor ..
LC74402E ,PIP ControllersFeatures. Horizontal resolution: 600 TV lines"l. Three D/A converters (for the Y, R-Y, and B-Y sign ..
LC7441 ,Picture-in-picture Controller for TVs and VCRsPin AssignmentsRAOUT YAOUTNC BAOUTVREF AVSSems en AVDDKLPFO' so CLAMPDAKLPFI 59 ESOLPFI se KOUTOLPF ..
LC74411N ,PIP ControllerFeatures• Horizontal resolution: 450 pixels*• Single-chip implementation of the three circuits requ ..
LC74411NE ,PIP ControllerOrdering number : EN*5519ACMOS LSILC74411N, LC74411NEPIP ControllerPreliminaryOverview Package Dime ..
LC7441N ,Picture-in-picture Controller for TVs and VCRsFeatures include stilllactive dis-play, white/color frame, F1xedlvariable (screen)positioning, and ..
L9654
Quad squib driver and dual sensor interface for safety application
November 2013 DocID14218 Rev 3 1/59
L9654Quad squib driver and dual sensor interface
ASIC for safety application
Datasheet - production data
Features 4 deployment drivers sized to deliver 1.2 A
(min) for 2 ms (min) and 1.75 A (min) for
1ms (min). Independently controlled high-side and low-
side MOS for diagnosis Analog output available for resistance Squib short to ground, short to battery and
MOS diagnostic available on SPI register Capability to deploy the squib with 1.2 A (min.)
or 1.75 A under 35 V load-dump condition and
the low-side MOS is shorted to ground Capability to deploy the squib with 1.2 A (min.)
at 6.9 V VRES and 1.75 A at 12 V VRES. Interface with 2 satellite sensors Programmable independent current trip points
for each satellite channel Support Manchester protocol for satellite
sensors Supports for variable bit rate detection Independent current limit and fault timer
shutdown protection for each satellite output Short to ground and short to battery detection
and reporting for each satellite channel 5.5 MHz SPI interface Satellite message error detection Low voltage internal reset 2 kV ESD capability on all pins Package: 48 lead LQFP Technology: ST Proprietary BCD5s (0.57 μm)
DescriptionL9654 is intended to deploy up to 4 squibs and to
interface up to 2 satellites.
Squib drivers are sized to deploy 1.2 A (min.) for ms (min.) during load dump and 1.75 A (min.)
for 1 ms (min.) during load dump.
Diagnostic of squib driver and squib resistance
measurement is controlled by micro controllers.
Satellite interfaces support Manchester decoder
with variable bit rates.
Table 1. Device summary
Order code Package PackingL9654 LQFP48 Tray
L9654TR LQFP48 Tape and reel
Contents L96542/59 DocID14218 Rev 3
Contents Block diagram and application schematic . . . . . . . . . . . . . . . . . . . . . . . 71.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.1 DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 Power on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3 RESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 MSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 IREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Deployment and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8.1 Chip select (CS_A, CS_D, CS_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8.2 Serial clock (SCLK, SCLK_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8.3 Serial data output (MISO, MISO_A) . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.8.4 Serial data input (MOSI, MOSI_A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.9 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.9.1 Arming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.10 DEPEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.10.1 Deployment driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.10.2 Continuity diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.10.3 Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DocID14218 Rev 3 3/59
L9654 Contents4.10.4 Short to ground and open circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.10.5 Resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.10.6 MOS diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.10.7 Low-side MOS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.10.8 High-side MOS diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.10.9 Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.11 Deployment driver SPI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.11.1 Deployment driver MOSI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.11.2 Deployment driver register mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.11.3 Deployment driver command mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.11.4 Deployment driver diagnostic mode . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.11.5 Deployment driver monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.11.6 Deployment driver MISO bit definition . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.11.7 Deployment driver register mode response . . . . . . . . . . . . . . . . . . . . . .39
4.12 MISO register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.12.1 Deployment driver command mode response . . . . . . . . . . . . . . . . . . . .41
4.12.2 Deployment driver diagnostic mode response . . . . . . . . . . . . . . . . . . . .42
4.12.3 Deployment driver status response . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.12.4 Deployment driver SPI fault response . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.13 Arming SPI bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.13.1 Arming MOSI_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.13.2 ARM[01..23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.13.3 ARM[01..23]* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.13.4 Arming MISO_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.13.5 ARM[01..23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.14 Satellite sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.14.1 Current sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.14.2 Manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.14.3 Communication protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.14.4 "A" protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.14.5 "B" variable length protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.14.6 FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.14.7 Satellite continuity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.14.8 Message waiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.14.9 Satellite serial data input (MOSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.14.10 Satellite MOSI bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.14.11 Satellite module configuration register (CH1 only) . . . . . . . . . . . . . . . .50
Contents L96544/59 DocID14218 Rev 3
4.14.12 Channel configuration registers (CCR1, CCR2, CCR3, CCR4) . . . . . . .51
4.14.13 SPI MISO bits layout for configuration report . . . . . . . . . . . . . . . . . . . .55
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DocID14218 Rev 3 5/59
L9654 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Table 4. Maximum operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. DC specification general. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 7. DC specification: deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 8. Satellite interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 9. AC specification: deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Table 10. AC specifications: satellite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 11. SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 12. SPI transmission during a deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 13. Deployment driver SPI response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 14. MOSI bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 15. MOSI mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 16. MOSI register mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 17. Pulse stretch timer table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 18. MOSI command mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 19. MOSI diagnostic mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Table 20. Channel selection decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 21. MOSI monitor mode message definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Table 22. MISO bit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 23. MISO mode bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 24. MISO register mode response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 25. MISO register mode response summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 26. MISO command mode response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 27. MISO diagnostic mode response definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Table 28. MISO status response definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 29. MISO SPI fault response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 30. Arming MOSI_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 31. Arming MISO_A bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 32. Satellite MOSI bits layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Table 33. MOSI satellite interface registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 34. Master configuration register definition (CH1 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Table 35. Channel configuration register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Table 36. Current ranges supported are given in following table . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 37. Satellite/decoder control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 38. "B" protocol configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 39. Bit time selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 40. Mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 41. SPI mode selects reply for satellite channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 42. Satellite MISO bits definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 43. SPI MISO bits layout when reporting FIFO data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 44. MISO Manchester message data definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 45. Status bits definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 46. Satellites fault codes definition supporting "A" protocol . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 47. Satellites fault codes definition supporting "B" protocol . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 48. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
List of figures L9654
6/59 DocID14218 Rev 3
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 2. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 3. MOS settling time and turn-on time 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 4. MOS settling time and turn-on time 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5. SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 6. SPI timing measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 7. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 8. Arming daisy-chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 9. Arming SPI transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 10. Deployment drivers diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 11. Deployment sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 12. Deployment flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 13. Deployment driver diagnostic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 14. Continuity diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 15. Resistance measurement flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 16. Low-side diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Figure 17. High-side driver diagnostic flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 18. Satellite interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 19. Manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 20. Manchester decoding using satellite protocol as an example. . . . . . . . . . . . . . . . . . . . . . .47
Figure 21. "A" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 22. "B" satellite protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 23. LQFP48 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
DocID14218 Rev 3 7/59
L9654 Block diagram and application schematic Block diagram and application schematic
1.1 Block diagram
Figure 1. Block diagram
1.2 Application schematic
Figure 2. Application schematic
Pin description L9654
8/59 DocID14218 Rev 3
2 Pin description
Table 2. Pin function
Pin # Pin name Description I/O type Reset state MISO_A Arming SPI data out Output Hi-Z NC No connect - - RESETB Reset pin Input Pullup GND Signal ground (analog & digital) - - VDD VDD supply voltage Input - NC No connect - - CS_A SPI chip select for arming interface Input Pulldown CS_S SPI chip select for satellite interface Input Pulldown CS_D SPI Chip select for deployment driver Input Pulldown DEPEN Deployment enable Input Pulldown MOSI SPI data in Input Hi-Z
12,13 NC No connect - - MOSI_A Arming SPI data in Input Hi-Z SCLK_A Arming SPI clock Input Hi-Z SCLK SPI clock Input Hi-Z GND2 Power ground for loop channel 2 - - SQL2 Low-side driver output for channel 2 Output Pulldown SQH2 High-side driver output for channel 2 Output Hi-Z VRES2 Reserve voltage for loop channel 2 Input - VRES3 Reserve voltage for loop channel 3 Input - SQH3 High-side driver output for channel 3 Output Hi-Z SQL3 Low-side driver output for channel 3 Output Pulldown GND3 Power ground for loop channel 3 - - TEST Test pin Input Pulldown NC No connect - - V8BUCK Supply Voltage for Satellite Interface and Resistance
Measurement Input - NC No connect - - ICH2 Current sense output for channel 2 Output Hi-Z NC No connect - - ICH1 Current sense output for channel 1 Output Hi-Z NC No connect - - IREF External current reference resistor Output -
DocID14218 Rev 3 9/59
L9654 Pin description
2.1 Thermal data
Table 3. Thermal data
Symbol Parameter Value. Unit
Rth j-amb Thermal resistance junction-to-ambient 68 °C/W AOUT_GND Ground reference for AOUT - - AOUT Analog output for loop diagnostics Output Hi-Z NC No connect - - GND1 Power ground for loop channel 1 - - SQL1 Low-side driver output for channel 1 Output Pulldown SQH1 High-side driver output for channel 1 Output Hi-Z VRES1 Reserve voltage for loop channel 1 Input - VRES0 Reserve voltage for loop channel 0 Input - SQH0 High-side driver output for channel 0 Output Hi-Z SQL0 Low-side driver output for channel 0 Output Pulldown GND0 Power ground for loop channel 0 - - NC No connect - - MSG Message waiting Output Pulldown MISO SPI data out Output Hi-Z NC No connect - -
Table 2. Pin function (continued)
Pin # Pin name Description I/O type Reset state
Electrical specification L9654
10/59 DocID14218 Rev 3
3 Electrical specification
3.1 Maximum ratings
The device may not operate properly if maximum operating condition is exceeded.
Table 4. Maximum operating conditions
Symbol Parameter Value Unit
VDD Supply voltage 4.9 to 5.1 V
V8BUCK V8BUCK voltage 7 to 8.5 V
VRES VRES voltage (VRES0, VRES1, VRES2, VRES3) 35 V Discrete input voltage (RESETB, DEPEN, CS_A, CS_D, CS_S, SCLK,
SCLK_A, MOSI, MOSI_A, MISO, MISO_A) 0.3 to (VDD +0.3) V Junction temperature -40 to 150 °C
3.2 Absolute maximum ratings
Maximum ratings are absolute ratings; exceeding any one of these values may cause
permanent damage to the integrated circuit.
Table 5. Absolute maximum ratings
Symbol Parameter Value Unit
VDD Supply voltage -0.3 to 5.5 V
V8BUCK V8BUCK voltage 0.3 to 40 V
VRES VRES voltage (VRES0, VRES1, VRES2, VRES3) 0.3 to 40 V
SQL-H Squib high and low-side drivers (SQH0, SQH1, SQH2, SQH3,
SQL0, SQL1, SQL2, SQL3) 0.3 to 40 V Discrete input voltage (RESETB, DEPEN, CS_A, CS_D, CS_S, SCLK,
SCLK_A, MOSI, MOSI_A, MISO, MISO_A) -0.3 to 5.5 V
ICHx Satellite input voltage (ICH1, ICH2, ICH3, ICH4) -3 to 40 V Analog/digital outputs voltage (AOUT, IREF, MSG, IF3V3, IF4V4) -0.3 to 5.5 V Maximum steady-state junction temperature 150 °C
Tamb Ambient temperature -40 to 95 °C
Tstg Storage temperature -65 to 150 °C
DocID14218 Rev 3 11/59
L9654 Electrical specification
3.3 Electrical characteristics
3.3.1 DC characteristics
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40°C to +95°C.
Table 6. DC specification general
Symbol Parameter Test condition Min. Typ Max. Unit
VRST(1) VRST shall have a POR de-glitch timer.
Internal voltage reset VDD VDD drops until deployment drivers
are disabled
4.0 - 4.5 VVRST_L(2) VRST L shall have no timer.
2.1 - 3.0
IDD Input current VDD
Normal operation; ICH1-2 = 0 A 4.5 - 7.0Short to –0.3V on SQH; ICH1-2 = 0 A 4.2 - 7.9
Short to –0.3V on SQL; ICH1-2 = 0A 4.2 - 7.9
Deployment; ICH1-2 = 0A 4.2 - 7.9
RIREF_H Resistance threshold IREF - 20.0 - 60.0 kΩ
RIREF_L - 2.0 - 9.0 kΩ
VIH_RESETB Input voltage threshold
RESETB - - 2.0 V
VIL_RESETB - 0.8 - V
VHYS - 100 - 400 mV
VIH_DEPEN Input voltage threshold
DEPEN - - 2.0 V
VIL_DEPEN - 0.8 - - V
IPD Input pull-down current
DEPEN VIN = VIL to VDD 10 - 50 μA
VIH_TEST Input voltage threshold TEST- - - 3.6 V
VIL_TEST - 0.8 - - V
ITEST Input pull-down current TEST TEST = 5 V 1.0 - 2.5 mA
IPU Input pull-up current RESETB RESETB = VIH to GND 10 - 60 μA
IV8BUCK Current consumption
V8BUCK - 25 - 40 μA
VIH Input voltage threshold MOSI,
MOSI_A, SCLK, SCLK_A,
CS_S, CS_D, CS_A
Input Logic = 1 - - 2.0 V
VIL Input Logic = 0 0.8 - - V
VHYS - 100 - 400 mV
ILKG Input leakage current MOSI,
MOSI_A, SCLK, SCLK_A
VIN = VDD - 1 μA
VIN = 0 to VIH -1 - - μA
IPD Input pulldown current
CS_S, CS_D, CS_A VIN = VIL to VDD 10 - 50 μA
VOH Output voltage MISO,
MISO_A, MSG
IOH = -800 μA VDD–0.8 - - V
VOL IOL = 1.6 mA - - 0.4 V
IHI_Z Tri-state current MISO,
MISO_A,
MISO = VDD - - 1 μA
MISO = 0 V -1 - - μA
Electrical specification L9654
12/59 DocID14218 Rev 3
VRES = 6.5 to 40 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C.
Table 7. DC specification: deployment drivers
Symbol Parameter Test conditions Min. Typ Max. Units
VOH Output voltage AOUT High Saturation Voltage; IAOUT = -500μA VDD- - - V
VOL Low Saturation Voltage; IAOUT = +500μA - - 0.3 V Tri-state current AOUT AOUT = VDD - - 1 μA
AOUT = 0V -1 - - μA
ILKG Leakage current SQH
V8BUCK = VDD = 0, VRES = 36 V,
VSQH = 0 V - - 50 μA
ISTG V8BUCK = 18V; VDD = 5V; VSQH = -0.3V -5 - - mA
ILKG Bias current VRES(1) Not applicable during a diagnostic.
V8BUCK = 18 V; VDD = 5 V;
VRES = 36V; SQH shorted to SQL - - 10 μA
ILKG
Leakage current SQL
V8BUCK = VDD = 0, VSQL = 18 V -10 - 10 μA
ISTG V8BUCK = 18 V; VDD = 5V; VSQL = -0.3 V -5 - - mA
ISTB V8BUCK = 18 V; VDD = 5 V;
VSQL = 18 V - - 5 mA
IPD Pull-down current SQL VSQL = 1.8 V to VDD 900 - 1300 μA
IPD_SQH Pull-down current SQH VSQH = SBTH to VRES 900 - 1300 μA
VBIAS Diagnostics bias voltage ISQH = -1.5 mA (nominal: 2.0 V) 1.80 - 2.20 V
IBIAS Diagnostics bias current VSQH = 0V -7 - - IPD
VSTB Short to battery threshold (Nominal 3.0 V) 2.70 - 3.30 V
VSTG Short to ground threshold (Nominal 1.0 V) 0.90 - 1.10 V
VI_th MOS test load voltage
detection - 100 - 300 mV
ISRC
Resistance
measurement current
source
VDD = 5.0 V; V8BUCK = 7.0 V to 26.5 V 38 - 42 mA
ISINK Resistance measurement
current sink - 45 - 55 mA
RDSon Total high and low-side
MOS On resistance
High-side MOS + Low-side
MOS VRES = 6.9 V; I = 1.2 A @95 °C - - 2.0 Ω
RDSon High-side MOS on
resistance
VRES = 35 V; IVRES = 1.2 A;
Tamb = 95 °C - - 0.8 Ω
RDSon Low-side MOS on
resistance
VRES = 35 V; IVRES = 1.2 A;
Tamb = 95 °C - - 1.2 Ω
IDEPL_12A
Deploiment current
MOSI Register mode bit D10=”0”
RLOAD = 1.7 ΩVRES = 6.9 to 35 V 1.20 - 1.47 A
IDEPL_175A MOSI Register mode Bit D10=”1”
RLOAD = 1.7 ΩVRES = 12 to 35 V 1.75 - 2.14 A
ILIM Low-side MOS current
limit RLOAD = 1.75 Ω 2.15 - 3.5 A
RL RANGE Load resistance range(2) Test conditions for load resistance measurements - 10.0 Ω
DocID14218 Rev 3 13/59
L9654 Electrical specification
VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C.
Table 8. Satellite interface DC specifications
Symbol Parameter Test conditions Min Typ Max Unit
I_Lim Current limit
High-side short to -0.3 V (-)75 - (-)150 mA
High-side short to Battery - - 5 mA
V8BUCK =Vcc=0
measured @ V8BUCK - - 5 mA
Vhdp High-side voltage drop I=50 mA @105°C; V8BUCK=7.0V - - 1 V
I=25 mA @105°C; V8BUCK=7.0V - - 0.5 V
Itr Low to high transition current
threshold
SPI channel configuration
Bit <2:0≥111 54.00 - 66.00 mA
Bit <2:0≥110 43.65 - 53.35 mA
Bit <2:0≥101 35.10 - 42.90 mA
Bit <2:0≥100 28.80 - 34.20 mA
Bit <2:0≥011 24.85 - 29.15 mA
Bit <2:0≥010 20.25 - 24.75 mA
Bit <2:0≥001 17.10 - 20.90 mA
Bit <2:0≥000 14.85 - 18.15 mA
Ihyst Current threshold hysteresis
Sink current = Ithr at the output
(ICHX).
Ihyst=trip point high – trip point
low
0.05*Itr - 0.15*Itr mA
Vos Short to BAT feedback current V(ICHX)-V8BUCK<50 mV - - 25 mA
Olkg Output leakage current ICHX V=18 V @ pin under test - - 1 μA
Electrical specification L9654
14/59 DocID14218 Rev 3
3.3.2 AC characteristics
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1 V, V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C.
Table 9. AC specification: deployment drivers
Symbol Parameter Test conditions Min Typ Max Unit
tPOR POR de-glitch timer Timer for VRST 10 - 25 μs
TGLITCH De-glitch timer - 5 - 20 μs
ION Diagnostic current
DEPEN pins asserted ;Measured at
150 s from falling edge CS_D or
CS_A; See Figure 4
0.90 - IFINAL
tPULSE Pulse stretch timer See Table 17 0 - 60 ms
tP_ACC Pulse stretch timer accuracy- -20 - 20 %
tDEPLOY-2ms Deployment time VRES = 6.9 to 35 V(1) Application Information; Test is not performed at high voltage. - 2.5 ms
tDEPLOY-1ms Deployment time VRES = 12 to 35 V(1) 1 - 1.25 ms
tFLT_DLY Fault detection filter(2) Design Information Only 10 - 50 μs
ISLEW Rmeas current di/dt 10 % - 90 % of ISRC 2 - 8 mA/μs
tR_DLY Rmeas current delay From the falling edge of CS to 10%
of ISRC - 15 μs
tR_WAIT Rmeas wait time(2) Wait time before AOUT voltage is
stable for ADC reading - - 100 μs
tTIMEOUT MOS diagnostic on-time - - - 2.5 ms
tILIM SQL high current protection
timer - 90 - 110 μs
tPROP_DLY LS/HS MOS turn off
propagation delay(2)
Time is measured from the valid
LS/HS MOS fault to the LS/HS turn
off - 10 μs
15/59L9654 Electrical specification
Figure 3. MOS settling time and turn-on time 1
Figure 4. MOS settling time and turn-on time 2
Electrical specification L9654
16/59 DocID14218 Rev 3
VDD = 4.9 to 5.1 V; V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
Table 10. AC specifications: satellite
Symbol Parameter Test conditions Min Typ Max Unit
Osc Internal oscillator frequency Tested with 12.5 K 1% Iref resistor 4.45 - 5.55 MHz
Mdf De-glitch filter as a function of
protocol speed
Manchester Protocol Excluding
Osc tolerance
Bit<8:7 00
Bit<8:7 01
Bit<8:7 10
Bit<8:7 11
11.76%*Bit-
Time 23.53
% *Bit-
Time
Bitr
Minimum frequency operating
range
(Incoming messages fall
within this operating range is
guaranteed to be accepted by
the IC)
Channel configurations
Bit<8:7 00
Test at frq = 52.33 kHz
Test at frq =13.32 kHz
13.32 - 52.33 kHz
Bit<8:701
Test at frq =110.74 kHz
Test at frq = 26.32 kHz
26.32 - 110.74 kHz
Bit<8:710
Test at frq =164.20 kHz
Test at frq = 43.50 kHz
43.50 - 164.20 kHz
Bit<8:711
Test at frq =250.63 kHz
Test at frq = 62.66 kHz
62.66 - 250.63 kHz
Bitr
Maximum frequency
operating range
(Incoming messages fall
outside this operating range is
guaranteed to be rejected by
the IC)
Channel configurations
Bit<8:7 00
Test at frq>59.14 kHz
Test at frq <11.99 kHz
11.99 - 59.14 kHz
Bit<8:701
Test at frq>128.37 kHz
Test at frq <23.57 kHz
23.57 - 128.37 kHz
Bit<8:710
Test at frq>194.93 kHz
Test at frq <38.71 kHz
38.71 - 194.93 kHz
Bit<8:711
Test at frq>309.6 kHz
Test at frq <55.37 kHz
55.37 - 309.6 kHz
Idle Idle time Manchester 2 - Bit
Times
Flt Output fault timer I_sensor>I_lim 300 - 500 μs
DocID14218 Rev 3 17/59
L9654 Electrical specification
VRES = 6.5 to 35 V, VDD = 4.9 to 5.1V. V8BUCK = 7.0 V to 8.5 V, Tamb = -40 °C to +95 °C
All SPI timing is performed with a 200 pF load on MISO unless otherwise noted.
Table 11. SPI timing
No. Symbol Parameter Min Typ Max Unit fop Transfer frequency dc - 5.50 MHz tSCK SCLK, SCLK_A Period 181 - - ns tLEAD Enable Lead Time 65 - - ns tLAG Enable Lag Time 50 - - ns tSCLKHS SCLK, SCLK_A High Time 65 - - ns tSCLKLS SCLK, SCLK_A Low Time 65 - - ns tSUS MOSI, MOSI_A Input Setup Time 20 - - ns tHS MOSI, MOSI_A Input Hold Time 20 - - ns tA MISO, MISO_A Access Time - - 60 ns tDIS MISO, MISO_A Disable Time (1) Parameters tDIS and tHO shall be measured with no additional capacitive load beyond the normal test fixture capacitance on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time, and minimum capacitance on MISO is the worst case for output hold time. - 100 ns tVS MISO, MISO_A Output Valid Time - - 66 ns tHO MISO, MISO_A Output Hold Time (1) 0 - - ns tRO Rise Time (Design Information) - - 30 ns tFO Fall Time (Design Information) - - 30 ns tCSN CS_A, CS_D, CS_S Negated Time 640 - - ns
Figure 5. SPI timing diagram
Figure 6. SPI timing measurement
Functional description L9654
18/59 DocID14218 Rev 3
4 Functional description
4.1 Overview
L9654 is an integrated circuit to be used in air bag systems. Its main functions include
deployment of air bags, switched-power sources to satellite sensors, diagnostics of SDM
(Sensing Deployment Module) and arming inputs. L9654 supports 4 deployment loops, 2
satellite-sensor interfaces, and SPI arming inputs.
4.2 Power on reset (POR)
L9654 has a power on reset (POR) circuit, which monitors VDD voltage. When VDD voltage
falls below VRST for longer than or equal to tPOR, all outputs are disabled and all internal
registers are reset to their default condition.
When VDD falls below VRST_L, all outputs are disabled and all internal registers are reset to
their default condition. No delay filter shall be used along with VRST_L threshold.
If VDD voltage falls below VRST for less than tPOR, operation shall not be interrupted.
When VDD rises above VRST , the outputs are enabled. Before VDD reaches VRST, and during
tPOR, none of the outputs turn on.
4.3 RESETB
RESETB pin is active low. The effects of RESETB are similar to those of a POR event,
except during a deployment. When L9654 has a deployment in-progress, it ignores the
RESETB signal.
However, it shall shut itself down as soon as it detects a POR condition. When the
deployment is completed and the RESETB signal is asserted, the device disables its
outputs and resets its internal registers to their default states.
A de-glitch timer is provided to the RESETB pin. The timer protects this pin against spurious
glitches. UT48 neglects the RESETB signal if it is asserted for shorter than tGLITCH.
RESETB has an internal pull-up in case of open circuit. This pin has a de-glitch timer.
4.4 MSG
MSG pin is used to reflect the FIFO status. Its polarity can be configured as well as the
strategy of activation.
Polling mode: Message pin shall be active as soon as one of the 4 FIFO is not empty and
becomes inactive when all 4 FIFO are empty. A microcontroller can periodically monitor the
status of line to understand if there are data received from satellite.
Interrupt mode: Message pin shall be active as soon one of the 4 FIFO is not empty and
becomes inactive when an SPI communication on CS_S interface starts. At the end of the
SPI communication it shall be active if one of the 4 FIFO is not empty, otherwise it shall be
kept inactive. A microcontroller can wait until an edge is present on the line and manage the
data available in the FIFO.
DocID14218 Rev 3 19/59
L9654 Functional description
4.5 IREF
IREF pin shall be connected to VDD supply through a resistor, RIREF . When the device
detects the resistor on IREF pin is larger than RIREF_H or smaller than RIREF_L, it goes in
reset condition. All outputs are disabled and all internal registers are reset to their default
conditions.
4.6 Loss of ground
When GND pin is disconnected from PC-board ground, L9654 goes in reset condition. All
outputs are disabled and all internal registers are reset to their default conditions. A loss of
power-ground (GND0 – GND3) pin/s disables the respective channel/s. In other words, the
channel that loses its power ground connection is not able to deploy. The rest of the device
is not affected by a loss of power-ground condition.
AOUT_GND pin is a reference for AOUT pin. When AOUT_GND loses its connection the reset
loses it as well.
4.7 Deployment and reset
The following conditions reset and terminate deployments: Power On Reset (POR) IREF resistance is larger than RIREF_H or smaller than RIREF_L Loss of ground condition on GND pin
The following conditions are ignored when there is a deployment in-progress: RESETB Valid soft reset sequences
4.8 Serial peripheral interface (SPI)
The device contains a serial peripheral interface consisting of Serial Clock (SCLK,
SCLK_A), Serial Data Out (MISO, MISO_A), Serial Data In (MOSI, MOSI_A), and two Chip
Selects (CS_A, CS_D and CS_S). This device is configured as an SPI slave. The idle state
of the communication, Serial Clock (SCLK, SCLK_A) should be in low state.
Functional description L9654
20/59 DocID14218 Rev 3
Figure 7. SPI block diagram
L9654 has a counter to verify the number of clocks in SCLK and SCLK_A. If the number of
clocks in SCLK is not equal to 16 clocks while CS_D is asserted, it ignores the SPI message
and sends an SPI fault response. If the number of clocks in SCLK is not equal to 64 clocks
while CS_S is asserted, it ignores the entire SPI message and pushes the Bad SPI Bit
Count fault code into the FIFO. If the number of clocks in SCLK_A is not a multiple of 8, it
ignores the command in the arming shift register. Otherwise, the device latches-in the
command.
Figure 8. Arming daisy-chain configuration
Arming SPI interface is based on 8-bit data transfer. The device is capable of receiving a
multiple of 8-bit commands. The first byte of data coming out of MISO_A is the arming
status bits. The subsequent bits are the arming command bits received through MOSI_A
pin. Refer to below figure for an example of arming SPI transmission. This is an example of
arming SPI transmission based on the daisy-chain configuration.
In case of daisy chain connection for arming SPI, device works as following:
All devices IC_1, IC_2, IC_3 shift out data on the falling edge of SCLK_A for the first 8 bits
and shift out data on the rising edge of SCLK_A for the bits after 8 bits. Therefore μP , IC_3,
IC_2 strobe 24 bits on rising edge of SCLK_A: the first 8 bits are produced (by IC_3, IC_2, IC_1 respectively) on the falling edge of
SCLK_A. the remaining 16 bits are shifted out on the rising edge.
DocID14218 Rev 3 21/59
L9654 Functional description
Figure 9. Arming SPI transmission
4.8.1 Chip select (CS_A, CS_D, CS_S)
Chip-select inputs select L9654 for serial transfers. CS_A is independent of CS_D and CS_S.
CS_A can be asserted regardless of CS_D and CS_S. However, either CS_D or CS_S can
be asserted at any given time. If both CS_D and CS_S inputs are selected simultaneously,
the device ignores MOSI command. When chip-select is asserted, the respective
MISO/MISO_A pin is released from tri-state mode, and all status information is latched in
the SPI shift register. While chip-select is asserted, register data is shifted into
MOSI/MOSI_A pin and shifted out of MISO/MISO_A pin on each subsequent
SCLK/SCLK_A. When chip-select is negated, MISO/MISO_A pin is tri-stated. To allow
sufficient time to reload the registers, chip-select pin shall remain negated for at least tCSN.
Chip-select is also immune to spurious pulses of 50 ns or shorter (MISO/MISO_A may come
out of tri-state, but no status bits are cleared and no control bits are changed).
Chip-select inputs have current sinks on the pins, which pull these pins to the negated state
when an open circuit condition occurs. These pins have TTL level compatible input voltages
allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.8.2 Serial clock (SCLK, SCLK_A)
SCLK/SCLK_A input is the clock signal input for synchronization of serial data transfer. This
pin has TTL level compatible input voltages allowing proper operation with microprocessors
using a 3.3 to 5.0 volt supply. When chip select is asserted, both the SPI master and this
device shall latch input data on the rising edge of SCLK/SCLK_A. L9654 shift data out on
the falling edge of SCLK/SCLK_A. The SCLK/SCLK_A must be taken in idle state (LOW)
when the CS_A,CS_D,CS_S are in idle state (LOW). (a)
4.8.3 Serial data output (MISO, MISO_A)
MISO/MISO_A output pin shall be in a tri-state condition when chip select is negated. When
chip select is asserted, the MSB is the first bit of the word/byte transmitted on
MISO/MISO_A and the LSB is the last bit of the word/byte transmitted. This pin supplies a
rail to rail output, so if interfaced to a microprocessor that is using a lower VDD supply, the
appropriate microprocessor input pin shall not sink more than I OH(min) and shall not clamp
the MISO/MISO_A output voltage to less than V OH(min) while MISO/MISO_A pin is in a logic
“1” state. Only in daisy chain, it is needed to guarantee on SCLK_A a clock skew of 3ns maximum between any devices.
Functional description L9654
22/59 DocID14218 Rev 3
4.8.4 Serial data input (MOSI, MOSI_A)
MOSI/MOSI_A input takes data from the master processor while chip select is asserted.
The MSB shall be the first bit of each word/byte received on MOSI/MOSI_A and the LSB
shall be the last bit of each word/byte received. This pin has TTL level compatible input
voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply.
4.9 Deployment drivers
The on-chip deployment drivers are designed to deliver 1.2 A (mi.n) at 6.9 V VRES.
Deployment current is 1.2 A (min.) for 2 ms (min.). The high-side driver survives deployment
with 1.47 A, 35 V at VRES and SQL is shorted to ground for 2.5 ms. Minimum load
resistance is 1.7. At the end of a deployment, a deploy success flag is asserted via SPI.
Each VRES and GND connection are used to accommodate 4 loops that can be deployed
simultaneously.
Upon receiving a valid deployment condition, the respective SQH and SQL drivers are
turned on. SQH and SQL drivers are also turned on momentarily during a MOS diagnostic.
Otherwise, SQH and SQL are inactive under any normal, fault, or transient conditions. Upon
a successful deployment of the respective SQH and SQL drivers, a deploy command
success flag is asserted via SPI. Refer to "deployment sequence" Figure 10 for the valid
condition and the deploy success flag timing.
Figure 10. Deployment drivers diagram
The following power-up conditions are considered as normal operations . VRES input can
be connected to either a power supply output or an ignition voltage. VDD is connected to V output of power supply. When VRES is connected to the power supply, VDD voltage
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L9654 Functional description
reaches its regulation voltage before VRES voltage is stabilized. In this condition, the device
has the control of its internal logic and that prevents an inadvertent turn-on of the drivers.
When VRES is connected to the ignition, VRES voltage is stabilized before VDD reaches its
regulation voltage. In this condition, all drivers are inactive. A pull-down on the gates of high-
side drivers (SQH) is provided to prevent these drivers from momentarily turning-on. Any
loop driver fault conditions do not turn on the SQH and SQL drivers. Only a valid
deployment condition can turn on the respective SQH and SQL drivers.
4.9.1 Arming interface
The arming interface is used as a fail-safe to prevent inadvertent airbag deployment. Along
with deployment command, these signals provide redundancy. Pulse stretch timer is
provided for each channel/loop. Either ARM signal or deployment command shall start the
pulse stretch timer.
Arming interface has a dedicated 8-bit SPI interface.
When CS_A is negated, L9654 latches ARM signal from the shift register and starts the
pulse stretch timer for the respective channel/s. The device can deploy a channel, ONLY
when DEPEN is asserted and any of the following conditions are satisfied: the respective deployment command is sent during a valid pulse stretch timer, which is
initiated by ARM signal the respective SPI ARM command is sent during a valid pulse stretch timer, which is
initiated by deployment command
During a deployment, the device turns on the respective high-side (SQH) and low-side
(SQL) drivers for duration of tDEPLOY . When a deployment is initiated, it can’t be terminated,
except during a reset event.
Figure 11. Deployment sequence
When a deployment-enable command is sent through SPI, the pulse stretcher shall be
initiated immediately following the falling edge of CS_D. When another deployment-enable
command is sent before the timer for the previous command expired, the timer is refreshed.
Sending a deployment-disable command terminates the pulse stretch timer operation.
ONLY a timer operation started by a deployment-enable command can be terminated.
Functional description L9654 DocID14218 Rev 3
A deployment-en/disable command does not affect the timer operation started by arming
signal.
When an arming-enable command is sent through SPI, the pulse stretcher is initiated
immediately following the falling edge of CS_A. When another arming-enable command is
sent before the timer for the previous command expired, the timer is refreshed. Sending an
arming disable command terminate the pulse stretch timer operation. ONLY a timer
operation started by an arming-enable command can be terminated. An arming-en/disable
command does not affect the timer operation started by a valid deployment command.
Figure 12. Deployment flow chart . Once deployment is initiated it cannot be terminated. When a channel is
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L9654 Functional description
messages and their responses are summarized in the below table. The rest of the channels
shall resume their operations and respond to specific SPI commands.
During a deployment, the device ignores arming commands. and does not refresh or
terminate the pulse stretch timer when it receives an arming command.
Table 12. SPI transmission during a deployment
SPI MOSI SPI MISO(1) SPI MISO sent in the next SPI transmission.
Register mode SPI fault response MOSI register mode message shall be ignored
Command mode Command mode Execute for channels not in deployment; no effect
to deploying channel
Diagnostic mode SPI fault response MOSI diagnostic mode message shall be ignored
Monitor mode Status response Execute for all channels
4.10 DEPEN
DEPEN is a deployment enable input, which is an active high input. When this pin is
asserted, L9654 is able to turn on its high and low-side drivers upon receiving a valid
deployment command or a MOS diagnostic request. DEPEN cannot interrupt a deployment
that is already in-progress.
When DEPEN is negated, it inhibits the low-side and the high-side MOS from turning on
(inhibit the deployment). When a MOS diagnostic is requested, the device executes the
diagnostic even without the ability to turn on the MOS. It sets the proper SPI threshold bits.
SPI remains functional while this pin is pulled low.
When DEPEN is negated, SPI deploy command is prevented from initiating the pulse
stretch timer. Regardless of DEPEN, “SPI deploy command” status bits reports the state of
“SPI deploy command” bits sent in the previous SPI transfer. This feature is required so that
the processor can diagnose SPI deploy command bits with DEPEN negated.
Regardless of DEPEN, arming signal is able to initiate the pulse stretch timer. This feature is
used for the processor to diagnose the arming signal.
When the pulse stretch timer has been running, changes in the state of DEPEN do not affect
the pulse stretch timer. The pulse stretch timer is not affected regardless of the pulse stretch
timer being started by an arming signal or an SPI deploy command.
A de-glitch timer is provided to DEPEN pin. The timer protects this pin against spurious
glitches. The device neglects DEPEN signal if it is asserted/negated for shorter than GLITCH.
Notes
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4.10.1 Deployment driver diagnostic
L9654 is able to perform a short to battery, a short to ground, a resistance measurement
and a MOS diagnostics on its deployment drivers. A short to ground and an open circuit
conditions are distinguished using a resistance measurement. Here below is shown the
diagram of deployment driver diagnostic.
The diagnostic is performed when a valid SPI command is received. Each current source
(ISRC and IBIAS) and current sink (ISINK, IPD_SQH) is turned on or off by an SPI command.
IPD_SQH is turned on when IBIAS is turned on. This pull-down (IPD_SQH) is used to deplete
the charge left on the SQH and SQL capacitors. IPD is permanently connected to SQL. This
current sink pulls down SQL pin during an open circuit condition.
Diagnostic current source or sink and comparator or amplifier are independent. It is possible
to turn on or off the current source or sink on a specific channel, while monitoring the
comparator or amplifier on a different channel. This feature is used to run a short between
loop diagnostic.
Figure 13. Deployment driver diagnostic diagram
4.10.2 Continuity diagnostic
A continuity diagnostic includes a short to battery, a short to ground and an open circuit
diagnostic.
During a continuity diagnostic, IBIAS is switched on. On a normal loading condition, SQH
voltage is below SBTH threshold and SQL voltage is above SGTH threshold.
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L9654 Functional description
Figure 14. Continuity diagnostic flow chart
4.10.3 Short to battery
A short to battery condition is detected when the voltage on SQH is greater than SBTH
threshold voltage.
4.10.4 Short to ground and open circuit
A short to ground or an open circuit condition is detected when the voltage on SQL is less
than SGTH threshold voltage. A resistance measurement is utilized to differentiate between
a short to ground or an open circuit condition.
4.10.5 Resistance measurement
During a resistance measurement, both I SRC and I SINK are switched on. An analog voltage
on A OUT pin is provided. A OUT pin is a 5V analog pin, which is connected to the ADC input
of a processor. This pin provides the resistance-measurement voltage, which corresponds
to the voltage difference across SQH and SQL according to the following formula: aout = VDD /10 + R squib · Isrc · 10.
The accuracy in the range of R squib is classified as followings:
0 < R squib ≤ 3.5 Ω ±95 mV
3.5 < R squib ≤ 10 Ω ±5 %
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A low pass filter (10 kΩ + 330 pF) is recommended in order to cancel the noise caused by
internal offset compensation.
Figure 15. Resistance measurement flow chart
4.10.6 MOS diagnostics
During diagnostic, IBIAS is connected to SQH pin. In a normal condition, SQH voltage is
below SBTH and SQL voltage is higher than SGTH. Prior to turning on the MOS, the
processor is expected to check for a short to battery and a short to ground fault. This step is
intended to prevent a large amount of current from flowing through the MOS. Also, this step
is intended to precondition SQH and SQL pins prior to diagnostics. DEPEN pin is asserted
in order to turn on the low or high-side driver. If DEPEN is negated during diagnostic, the
MOS is not turned on and a fail MOS diagnostic is expected.
4.10.7 Low-side MOS diagnostic
When L9654 receives an SPI command to initiate the low-side driver diagnostic, verification
of following conditions is done before turning on the low-side driver: VSQL greater than SGTH threshold voltage VSQH less than SBTH threshold voltage
If both conditions above are satisfied, execution of low-side driver diagnostic is performed.
Otherwise, the low-side MOS diagnostic request is ignored and both bit D13 and bit D7 in
SPI diagnostic mode response are set. Upon detection of the following conditions, the
device turns the low-side driver off and terminates the diagnostic within the specified time,
tPROP_DLY. VSQL less than SGTH threshold voltage (VSQHx – VSQLx) greater than VI_TH VSQH greater than SBTH threshold voltage
The state of each comparator above is reported through SPI. When the device detects one
of the above conditions, the respective SPI status bit indicates that the condition is set. Any
of the above conditions is considered as normal in a low-side MOS diagnostic.
The low-side driver is turned off when tTIMEOUT is expired. A fault detection filter, tFLT_DLY, is
provided to protect against short-transients on SQH and SQL pins.
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L9654 Functional description
Figure 16. Low-side diagnostic flow chart
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4.10.8 High-side MOS diagnostic
When L9654 receives an SPI command to initiate the high-side MOS diagnostic, the
following conditions are verified before turning on the high-side MOS: VSQL greater than SGTH threshold voltage VSQH less than SBTH threshold voltage
If both conditions above are satisfied, the high-side MOS diagnostic is executed. Otherwise,
it is ignored and both bit D13 and bit D7 in SPI diagnostic are set.
Upon detection of the following conditions, the high-side driver is turned off and the
diagnostic, within the specified time, tPROP_DLY , is terminated VSQH greater than SBTH threshold voltage (VSQHx – VSQLx) greater than VI_TH VSQL less than SGTH threshold voltage
The state of each comparator above is reported through SPI. When L9654 detects one of
the above conditions, it sets the respective SPI status bit to indicate the condition. Any of the
above conditions is considered as normal in a high-side MOS diagnostic.
The high-side driver is turned off when tTIMEOUT is expired. A fault detection filter, tFLT_DLY, is
provided to protect against short-transients on SQH and SQL pins.
4.10.9 Loss of ground
When any of the power grounds (GND0 – 7) are lost, no deployment can occur to the
respective deployment channels. A loss of ground condition on one or several channels
does not affect the operation of the remaining channels.
When a loss of ground condition occurs, the source of the low-side MOS is floating. In this
case, no current flows through the low-side driver.
This condition is detected as a fault by a low-side MOS diagnostic. Also, the resistance
measurement result is on the low end of the resistance range.
