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L9610C
PWM POWER MOS CONTROLLER
L9610C
L9611 COctober 2000
PWM POWER MOS CONTROLLER. HIGH EFFICIENCY DUE TO PWM CONTROL
AND POWERMOS DRIVER. LOAD DUMP PROTECTION. LOAD POWER LIMITATION. EXTERNAL POWERMOS PROTECTION. LIMITED OUTPUT VOLTAGE SLEW RATE
DESCRIPTIONThe L9610C/11C is a monolithic integrated circuit
working in PWM mode as controller of an external
powerMOS transistor in High Side Driver configura-
tion.
Features of the device include controlled slope of
the leading and trailing edge of the gate driving vol-
tage, linear current limiting with protection timer, set-
table switching frequency fo, TTL compatible enable
function, protection status ouput pin. The device is
mounted in SO16 micropackage, and DIP16 pack-
age.
BLOCK DIAGRAM1/12
PIN CONNECTION (Top view)
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
L9610C - L9611C2/12
PIN FUNCTIONS
L9610C - L9611C3/12
ELECTRICAL CHARACTERISITCS (Tamb = – 40 °C to 85 °C ; 6 V < VS < 16 V unless otherwise specified)
Notes :1. fo = KF/CF. dVG/dt = Ks/Cs. tprot = KT CT.
FUNCTIONAL DESCRIPTIONPULSE WIDTH COMPARATOR
A ground compatible comparator generates the
PWM signal which controls the gate of the external
powerMOS.
The slopes of the leading and trailing edges of the
gate driving signal are defined by the external ca-
pacitor CS according to :
dVG/dt = KS/CS
This feature allows to optimize the switching speed
for the power and RFI performance best suited for
the application.
The lower limit of the duty cycle is fixed at 15 % of
the ratio between the input and the reference vol-
tage (see fig. 1). Input voltages lower than this value
disable the internal oscillator signal and therefore
the gate driver.
GROUND COMPATIBLE TRIANGLE
OSCILLATOR
The triangle oscillator provides the switching fre-
quency fo set by the external capacitor CF according
to :
fo = KF/CF
If the pin PWL (power limitation) is connected to
ground and Vs is higher than the PWL threshold
voltage, the duty cycle and the fo frequency are re-
duced : this allows to transfer a costant power to the
load (see fig. 2).
TIMER AND PROTECTION LATCH
When an overcurrent occurs, the device starts
charging the external capacitor CT ; the protection
time is set according to :
tprot = KT . CT
L9610C - L9611C4/12
After the overcurrent protection time is reached, the
powerMOS is switched-off ; this condition is latched
by setting an internal flip-flop and is externally moni-
tored by the low state of the MON pin.
To reset the latch the supply voltage has to fall below
VSL or the device must be switched off.
UNDER AND OVERVOLTAGE SENSE WITH
LOAD DUMP PROTECTION
The undervoltage detection feature resets the timer
and switches off the output driving signal when the
supply voltage is less than VSL.
If the supply voltage exceeds the max operating
supply voltage value, an internal comparator dis-
ables the charge pump, the oscillator and the exter-
nal powerMOS.
In both cases the thresholds are provided with suit-
able hysteresis values.
The load dump protection function allows the device
to withstand - for a limited time - high overvoltages.
It consists of an active clamping diode which limits
the circuit supply voltage to VCLAMP and an external
current limiting resistor R1. The maximum pulse
supply current (see abs. max. ratings is equal to
0.3A. Therefore the maximum load dump voltage is
given by :
VDUMP = VSC + 0.3R1
In this condition the gate of the powerMOS is held
at the GND pin potential and thus the load voltage
is :
VL = Vs - VCLAMP - VGS
Figure 1 : Typical Transfer Curve.
L9610C - L9611C5/12
Figure 2 : The Typical Waveforms for the Power Limitation Function.SHORT CIRCUIT CURRENT REGULATION
The maximum load current in the short circuit con-
dition can be chosen by the value of the current
sensing resistor RS according to :
ISC = VSI/RS
Two identical VS compatible comparators are pro-
vided to realize the short circuit protection.
After reaching the lower threshold voltage (typical
value VSI-10 mV), the first comparator enables the
timer and the gate is driven with the full continuous
pump voltage : when the upper threshold voltage
value is reached the second comparator maintains
the chosen ISC driving the NMOS gate in continuous
mode.
This function - showed in fig. 3 - speeds up the
switch on phase for a lamp as a load.
BANDGAP VOLTAGE REFERENCE
The circuit provides a reference voltage which may
be used as control input voltage through a resistive
divider. This reference is protected against the short
circuit current.
CHARGE PUMP
The charge pump circuit holds the N-MOS gate
above the supply voltage during the ON phase. This
circuit consists of an RC astable which drives a com-
parator with a push-pull output stage. The external
charge pump capacitor CP must be at least equal to
the NMOS parasitic input capacitance.
For fast gate voltage variation CP must be increased
or the bootstrap function can be used. The bootstrap
capacitor should be at least 10 times greater than
the powerMOS parasitic capacitance.
The charge pump voltage VPUMP can reach to :
VPUMP = 2 VS - VBE - VCESAT
The circuit is disabled if the supply voltage is higher
than VSH.
L9610C - L9611C6/12
