L9352B ,INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCHL9352BINTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH■ L9352B Quad low-side switch■ 2 x 5A designed ..
L9362 ,QUAD LOW SIDE DRIVERL9362QUAD LOW SIDE DRIVER■ QUAD LOW-SIDE DRIVER FOR AUTOMO-TIVE APPLICATION■ CURRENT FEEDBACK OUTPU ..
L9362013TR ,QUAD LOW SIDE DRIVERBLOCK DIAGRAMVCCVCCROLVCC==TriggerOUT1NON1dV/dtDriverControlS=Reset OUT2NON2ROUT3Overtemp.NON3NON1O ..
L9363 ,QUAD INTEGRATED LOW SIDE DRIVERBLOCK DIAGRAM
L V 15 ‘15:: DQRINA
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L9380 ,TRIPLE HIGH-SIDE MOSFET DRIVERELECTRICAL CHARACTERISTICS (7V ≤ V ≤ 18.5V; -40°C ≤ T ≤ 150°C, unless otherwise specified.)S JSymbo ..
L9380-TR ,TRIPLE HIGH-SIDE MOSFET DRIVERfeatures a current source toassure defined high status when the pin is open.9 EN Enable logic signa ..
LC7385. ,DTMF ReceiverAbsolute Maximum Ratings at Ta=25– 2˚C, V =0VSSPl arameter Ss ymbo Cs ondition Rt ating UniMV aximu ..
LC7385M ,DTMF ReceiverFeatures 18 10• Single +5V power supply.• Decodes all 16 DTMF digits.• Built-in differential input ..
LC7385M- ,DTMF ReceiverPin Assignment16 15 14 13 12 11 1018 17912 3 45 67 8Pin FunctionsPe in No. NO amIn / Descriptio+1N ..
LC73861 ,DTMF Receiver LSIElectrical Characteristics at Ta = 25°C ± 2°C, V =5V,V =0V,f = 4.194304 MHzDD SS OSCParameter Symbo ..
LC73872 ,DTMF ReceiverFeatures u d. Detects all 16 DTMF signals. -"i1"1-'un I-; T. Includes on-chip all filters required ..
LC73872 ,DTMF ReceiverFeatures u d. Detects all 16 DTMF signals. -"i1"1-'un I-; T. Includes on-chip all filters required ..
L9352B
INTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
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L9352BFebruary 2004 L9352B Quad low-side switch 2 x 5A designed as conventional switch 2 x 2.5A designed as switched current-regulator Low ON-resistance 4 x 0.2Ω (typ.) Power SO-36 - package with integrated
cooling area Integrated free-wheeling and clamping Z-diodes Output slope control Short circuit protection Selective overtemperature shutdown Open load detection Ground and supply loss detection External clock control Recirculation control Regulator drift detection Regulator error control Regulator resolution 5mA Status monitoring Status push-pull stages Electrostatic discharge (ESD) protection
DESCRIPTIONThe L9352B is an integrated quad low-side power
switch to drive inductive loads like valves used in
ABS systems. Two of the four channels are current
regulators with current range from 0mA to 2.25A..
All channels are protected against fail functions.
They are monitored by a status output.
Figure 1. Pin ConnectionINTELLIGENT QUAD (2X5A/2X2.5A) LOW-SIDE SWITCH
L9352B
Figure 2. Block Diagram
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L9352B
PIN DESCRIPTION
L9352B
ABSOLUTE MAXIMUM RATINGS The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is sub-
jected to conditions which are beyond these values.
THERMAL DATA(1) This parameter will not be tested but assured by design
5/21
L9352B
OPERATING RANGE
ELECTRICAL CHARACTERISTCS: (Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
L9352B
ELECTRICAL CHARACTERISTCS: (continued)(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
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L9352B(1) This parameter will not be tested but assured by design.
(2) Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW"
(3) Digital filtered with external clock, only functional test
ELECTRICAL CHARACTERISTCS: (continued)(Vs = 4.8 to 18V; Tj = -40 to 150°C unless otherwise specified)
L9352B Functional Description
1.1 OverviewThe L9352B is designed to drive inductive loads (relays, electromagnetic valves) in low side configuration. In-
tegrated active Zener-clamp (for channel1 and 2) or free wheeling diodes (for channel 3 and 4) allow the recir-
culation of the inductive loads. All four channels are monitored with a status output. All wiring to the loads and
supply pins of the device are controlled. The device is self-protected against short circuit at the outputs and over-
temperature. For each channel one independent push-pull status output is used for a parallel diagnostic func-
tion.
Channel 3 and 4 work as current regulator. A PWM signal on the input defines the target output current. The
output current is controlled through the output PWM of the power stage. The regulator limit of 90% is detected
and monitored with the status signal. The current is measured during recirculation phase of the load.
A test mode compares the differences between the two regulators. This “drift” test compares the output PWM
of the regulators. By this feature a drift of the load during lifetime can be detected.
1.2 Input CircuitsThe INput, CLK, TEST and ENable inputs, are active high, consist of Schmidt triggers with hysteresis. All inputs
are connected to pull-down current sources.
1.3 Output Stages (not regulated) Channel 1 and 2The two power outputs (5A) consist of DMOS-power transistors with open drain output. The output stages are
protected against short circuit. Via integrated Zener-clamp-diodes the overvoltage of the inductive loads due to
recirculation are clamped to typ. 52V for fast shut off of the valves. Parallel to the DMOS transistors there are
internal pull-down current sources. They are provided to assure an open load condition in the OFF-state. With
EN=low this current source is switched off, but the open load comparator is still active.
1.4 Current-Regulator-Stages Channel 3 and 4The current-regulator channels are designed to drive inductive loads. The target value of the current is given by
the duty cycle (DC) of the 2kHz PWM input signal. The following figure shows the relation between the input
PWM and the output current and the specified accuracy.
Figure 3. Input PWM to output current range
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L9352BThe ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock.
For requested precision of the output current the ratio between the frequencies of the input signal and the ex-
ternal 250kHz clock has to be fixed according to the graph shown in Fig.
Figure 4. Current accuracy according to the input and clock frequency ratioThe theoretical error is zero for fCLK / fIN = 125.
If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For
a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision appli-
cations the clock frequency and the input frequency have to be correlated.
The output current is measured during the recirculation of the load. The current sense resistor is in series to the
free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output
remains low for the rest of the input cycle.
The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is
3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output
and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of
the power is 256µs after the first negative edge of the input signal.
As regulator a digital PI-regulator with the Transfer function for:
KI: and KP: 0.96 for a sampling time of 256us is realised.
To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current
value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90%
during the regulation. The status output gets low if the target current value is not reached within the regulation
error delay time of tRE=10ms.
1.5 Protective CircuitsThe outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock
is monitored by a clock watchdog. This clock watchdog detects a minimal frequency fCLK,min and wrong clock
duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected
0.126–---------------
L9352Bagainst recirculation errors, when D3 or D4 is not connected. All these error conditions shut off the power stage
and invert the status output information.
1.6 Error DetectionThe status outputs indicate the switching state under normal conditions (status LOW = OFF; status HIGH = ON).
If an error occurs, the logic level of the status output is inverted, as listed in the diagnostic table below. All ex-
ternal errors, for example open load, are filtered internally. The following table shows the detected errors, the
filter times and the detection mode (on/off).
EN&IN=low means that at least one between enable and input is low. For the inputs IN=low means also no input
PWM. For the regulator input period longer than TDreg and for the standard channel input period longer thanTD.
A detected error is stored in an error register. The reset of this register is made with a timer TD. With this ap-
proach all errors are present at the status output at least for the time TD.
All protection functions like short circuit of the output, overtemperature, clock failure or power-GND-loss in ON
condition are stored into an internal “fail” register. The output is then shut off. The register must be reset with a
low signal at the input. A “low signal” means that the input is low for a time longer than TD or TDReg for the re-
ulated channel, otherwise it is interpreted as a PWM input signal and the register is left in set mode.
Signal-GND-loss and VS-loss are detected in the active on mode, but they do not set the fail register. This type
of error is only delayed with the standard timer tlf function.
Open load is detected for all four channels in on- and off-state.
Open load in off condition detects the voltage on the output pin. If this voltage is below 0.33 * VS the error reg-
ister is set and delayed with TD. A sink current stage pull the output down to ground, with EN high. With EN low
the output is floating in case of openload and the detection is not assured. In the ON state the load current is
monitored by the non-regulated channels. If it drops below the specified threshold value IQU an open load is
detected and the error register is set and delayed with TD. A regulated channel detects the open load in the on
state with the current regulator error detection. If the output PWM reaches 90% for a time longer than tRE than
an error occurs. This could happen when no load is connected, the resistivity of the load is too high or the supply
voltage too low.
A clock failure (clock loss) is detected when the frequency becomes lower than fCLK,min. All status outputs are
set on error and all power outputs are shut off. The status signals remain in their state until the clock signal is
present again. A clock failure during power on of VCC is detected only on the regulated channels. The status
outputs of the channel 1 and 2 are low in this case.
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L9352B
1.7 Drift Detection (regulated channels only)The drift detection is used to compare the two regulated channels during regulation. This “Drift” test compares
the output PWM of the regulators. The resistivity of the load influences the output PWM. The approximated for-
mula for the output current below shows the dependency of the load resistor to the output PWM. In this formula
the energy reduction during the recirculation is not taken into account. The real output PWM is higher. The test-
mode is enabled with IN, EN and TEST high. With an identical 2kHz PWM-Signal connected to the IN-inputs
the output PWM must be in a range of ±14.3%. If the difference between the two on-times is more than ±14.3%
of the expected value an error is detected and monitored by the status outputs, in the same way as described
above, but a drift error will not be registered and also not delayed with TD as other errors
A 7bit output-PWM-register is used for the comparison. The register with the lower value is subtracted from the
higher one. This result is multiplied by four and compared with the higher value.
1.8 Other Test modesThe test pin is also used to test the regulated channels in the production. With a special sequence on this pin
the power stages of the regulated channels can be controlled direct from the input. No status feedback of the
regulated channels is given. The status output is clocked by the regulator logic. The output sequence is a indi-
cation of a proper logic functionality. The following table shows the functionality of this special test mode
For more details about the test lcondition four see timing diagram.
IOUT VBAT RON+---------------------------- PWM⋅=
Drift Definition:
Drift = PWM(1+E) - PWM (1-E) = 2PWM E
Drift * 4 < PWM (1+E)
with E >14.3% a drift is detected
E.. not correlated Error of the channels
%PWM ... Corresponding ideal output PWM to a given input PWM
