L6997 Fast Delivery |IC PHOENIX CO.,LIMITED

L6997 ,STEP DOWN CONTROLLER FOR LOW VOLTAGES OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6997S ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSElectrical Characteristics (continued)(V = V = 3.3V; T = 0°C to 85°C unless otherwise specified)CC ..
L6997STR ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L702B ,2A QUAD DARLINGTON SWITCHL7022A QUAD DARLINGTON SWITCHSUSTAINING VOLTAGE: 70 V2 A OUTPUTHIGH CURRENT GAINIDEAL FOR DRIVING S ..
L702N ,2A QUAD DARLINGTON SWITCHABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVCEX Collector-emitter Voltage (input open) 90 V ..
L7203 ,SMOOTH DRIVE SPINDLE MOTOR FOR OPTICAL DRIVE APPLICATION WITH POWER INTEGRATEDBLOCK DIAGRAMPRSSRCLOW VOLTAGEDETECTORAGNDDGNDApril 20011/13L7203 (continued)DESCRIPTIONSMOOTH DRIV ..
LC4128V-5T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5T144C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5TN128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T144I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

L6997
STEP DOWN CONTROLLER FOR LOW VOLTAGES OPERATIONS
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L6997
May 2004 FEATURES FROM 3V TO 5.5V VCC RANGE MINIMUM OUTPUT VOLTAGE AS LOW AS
0.6V 1V TO 28V INPUT VOLTAGE RANGE CONSTANT ON TIME TOPOLOGY VERY FAST LOAD TRANSIENTS 0.6V, ±1% VREF SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT, AVAILABLE
ALSO IN SINKING MODE REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600µA TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGTH LOADS 94% EFFICIENCY FROM 3.3V TO 2.5V APPLICATIONS NETWORKING DC/DC MODULES DISTRIBUTED POWER MOBILE APPLICATIONS CHIP SET, CPU, DSP AND MEMORIES
SUPPLY DESCRIPTION
The device is a high efficient solution for networking
dc/dc modules and mobile applications compatible
with 3.3V bus and 5V bus.
It's able to regulate an output voltage as low as 0.6V.
The constant on time topology assures fast load tran-
sient response. The embedded voltage feed-forward
provides nearly constant switching frequency opera-
tion in spite of a wide input voltage range.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The remote sensing improves the static and dynamic
regulation, recovering the wires voltage drop.
Pulse skipping technique reduces power consump-
tion at light loads. Drivers current capability allows
output currents in excess of 20A.
STEP DOWN CONTROLLER
FOR LOW VOLTAGE OPERATIONS
Figure 2. Minimum Component Count Application
REV. 4
Figure 1. Package
Table 1. Order Codes
L6997
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Figure 3. Pin Connection (Top View)
Table 4. Pin Function
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L6997
Table 5. Electrical Characteristics
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
Table 4. Pin Function (continued)
L6997
Table 5. Electrical Characteristics (continued)
(VCC = VDR = 3.3V; Tamb = 0°C to 85°C unless otherwise specified)
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L6997
Figure 4. Functional & Block Diagram
L6997 DEVICE DESCRIPTION
4.1 Constant On Time PWM topology
Figure 5. Loop block schematic diagram
The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time
duration forced by the one-shot generator. The On Time is directly proportional to VSENSE pin voltage and in-
verse to OSC pin voltage as in Eq1:
(1)
where KOSC = 180ns and τ is the internal propagation delay time (typ. 40ns). The system imposes in steady
state a minimum On Time corresponding to VOSC = 1V. In fact if the VOSC voltage increases above 1V the cor-
responding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a
steady-state switching frequency FSW independent of VIN. It results:
(2)
where
(3)
(4)
The above equations allow setting the frequency divider ratio αOSC once output voltage has been set; note
that such equations hold only if VOSC<1V. Further the Eq2 shows how the system has a switching frequen-
cy ideally independent from the input voltage. The delay introduces a light dependence from VIN. A mini-
mum Off-Time constraint of about 500ns is introduced in order to assure the boot capacitor charge and toON K OSC SENSE OSC -------------------- τ+=SW OUTIN
---------------1ON
----------- α OSC OUT
----- ---------- 1 OSC
--------------- α OSC→ fSWK OSCα OUT== = OSC OSCIN-------------- R22 R1+--------------------== OUTFB OUT
--------------- R43 R4+--------------------==
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L6997
limit the switching frequency after a load transient as well as to mask PWM comparator output against
noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity.
4.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage
(0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid
noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns
off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4.
The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of
DC error. Further the system regulates the output voltage valley value not the average, as shown in Figure 6.
So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To com-
pensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output
voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal in-
tegrator amplifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides
an AC path for output ripple.
Figure 6. Valley regulation
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in order to compensate the total static error. A voltage clamp within the device forces anINT pin voltage
range (VREF-50mV, VREF+150mV). This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherwise the integrator will operate out of its linear range. Choose
CINT1 according to the following equation:
(5)
where gINT=50 µs is the integrator transconductance, αOUT is the output divider ratio given from Eq4 and FU is
the close loop bandwidth. This equation holds if CINT2 is connected between INT pin and ground. CINT2 is given
by: INT1INTα OUT⋅πFu⋅⋅-------------------------------=
L6997
(6)
Where ΔVOUT is the output ripple and ΔVINT is the required ripple at the INT pin (100mV typ).
Figure 7. Integrator loop block diagram
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hys-
teretic system the frequency can change with some parameters. For example, while in a standard fixed switch-
ing frequency topology, the increase of the losses (increasing the output current, for example) generates a
variation in the On Time and Off Time, in a fixed On Time topology , the increase of the losses generates only
a variation on the Off Time, changing the switching frequency. In L6997 is implemented the voltage feed-forward
circuit that allows constant switching frequency during steady-sate operation and withinthe input range variation.
Any way there are many factors affecting switching frequency accuracy in steady-state operation. Some of
these are internal as dead times, which depends on high side MOSFET driver. Others related to the external
components as high side MOSFET gate charge and gate resistance, voltage drops on supply and ground rails,
low side and high side RDSON and inductor parasitic resistance.
During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
4.3 Transition from PWM to PFM/PSK
To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off phase; the on phase is the same. In PFM after a On cycle the system turns-on the
low side MOSFET until the inductor current goes down zero, when the zero-crossing comparator turns off the
low side MOSFET. In PWM mode, after On cycle, the system keeps the low side MOSFET on until the next turn-
on cycle, so the energy stored in the output capacitor will flow through the low side MOSFET to ground. The
PFM mode is naturally implemented in an hysteretic controller enabling the zero current comparator by en-
abling, in fact in PFM mode the system reads the output voltage with a comparator and then turns on the high
side MOSFET when the output voltage goes down to reference value. The device works in discontinuous mode INT2 INT1
--- ------------- V OUTΔINT
------------------=
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L6997
at light load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is
around half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher
the inductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower
the transient response is. The PFM waveforms may appear more noisy and asynchronous than normal opera-
tion, but this is normal behaviour mainly due to the very low load. If the PFM is not compatible with the applica-
tion it can be disabled connecting to VCC the NOSKIP pin.
4.4 Softstart
After the device is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart
is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start
range for the VSS voltage (where the output current limit increase linearly) is from 0.6V to 1V. In this range an
internal current source (5µ A Typ) charges the capacitor on the SS pin; the reference current (for the current limit
comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5µA (Typ.). When SS
voltage is close to 1V the maximum current limit is active. Output protections OVP & UVP are disabled until the
SS pin voltage reaches 1V (see figure 8).
Once the SS pin voltage reaches the 1V value, the voltage on SS pin doesn't impact the system operation any-
more. If the SHDN pin is turned on before the supplies, the power section must be turned on before the logic
section. While if the supplies are applied with the SHND pin off, the start up sequence doesn't meter.
Figure 8. Soft -Start Diagram
Because the system implements the soft start by controlling the inductor current, the soft start capacitor should
be selected based on of the output capacitance, the current limit and the soft start active range (ΔVSS).
In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before
the soft start voltage reaches the under voltage value (1V). After this UVP and OVP are enable.
The time necessary to charge the SS capacitor up to 1V is given by:
(7)
In order to calculate the output voltage chargin time it should be considered that the inductor current function
can be supposed linear function of the time.
(8)SSCSS() 1V
Iss-------- CSS⋅=L t,CSS() R ilim/R dson K ILIMISSt⋅⋅ ⋅()SSCSS⋅Δ ()------------ ----------------------------------------------------- ----------=
L6997
so considering zero the output load the output voltage is given by:
(9))
indicating with Vout the final value, the output charging time can be estimated as:
(10)
the minimum CSS value is given imposing this condition:
Tout =TSS (11)
4.5 Current limit
The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and com-
pares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the high side MOSFET Turn On.
To properly set the current limit threshold, it should be noted that this is a valley current limit. The Average cur-
rent depends on the inductor value, VIN VOUT and switching frequency.
The average output current in current limit is given by:
(12)
Thus, to set the current threshold, choose RILIM according to the following equation:
(13)
In overcurrent conditions the system keeps the current constant until the output voltage meets the undervoltage
threshold. The negative valley current limit, for the sink mode, is set automatically at the same value of the pos-
itive valley current limit. The average negative current limit differs from the positive average current limit by the
ripple current; this difference is due to the valley control technique.
The current limit system accuracy is function of the precision of the resistance connected to the ILIM pin and
the low side MOSFET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 1V
to ensure the system linearity.
Figure 9. Current limit schematicout t,CSS() Qt,CSS()out
------------- ------------ Rilim/R dsonK ILIMISSt2⋅⋅ ⋅()out VSS CSS2⋅⋅Δ⋅ ()-- ----------------------------------------------------- ----------------------==outCSS() Vout Cout VSSCSS2⋅⋅Δ⋅⋅ilim/R dsonK ILIMISS⋅⋅ ()----------------------- --------------- --------------- ----------------
0.5 OUTCL I max valley IΔ-----+= max valley ILim
Rdson
-----------------K ILIM⋅=
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L6997
4.6 Protection and fault
The load protection is realized by using the VSENSE pin. Both OVP and UVP are latched, and the fault condition
is indicated by the PGOOD and the OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ)
of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched:
low side MOSFET and, high side MOSFET are turned off and PGOOD goes low. In case the system detects an
overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted the SHDN pin, or by removing the sup-
ply, and restarting the devicewith the correct sequence.
4.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sitions. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
drivers have the adaptive anti-cross-conduction protection, which prevents from having bothhigh side and low
side MOSFET on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the PHASE pin begins to fall; the low side MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge the switching frequency and the driver voltage. So the power dissipation of the device is
function of the external power MOSFET gate charge and switching frequency.
(14)
The maximum gate charge values for the low side and high side are given by:
(15)
(16)
Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is QMAXLS = 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, approximately 0.5 ohms.
This prevents undesired LS MOSFET Turn On during the fast rise-time of the pin PHASE, due to the Miller ef-
fect.
When the 3.3V bus is used to supply the drivers, ULTRA LOGIC LEVEL MOSFETs should be selected , to be
sure that the MOSFETs work in properly way. driver Vcc Q gTOTF SW⋅⋅= MAXHS SW0SW
------------- 75nC⋅= MAXLS SW0SW
------------- 125nC⋅=
L6997 APPLICATION INFORMATION
5.1 5A Demo board description
The demo board shows the device operation in this condition: VIN from 3.3V to 5V, IOUT=5A VOUT=1.25V. The
evaluation board let use the system with 2 different voltages (VCC the supply for the IC and VIN the power input
for the conversion) so replacing the input capacitors the power input voltage could be also 35V. When instead
the input voltage (VIN) is equal to the VCC it should be better joining them with a 10Ω resistor in order to filter the
device input voltage. On the topside demo there are two different jumpers: one jumper, near the OVP and POW-
ER GOOD test points, is used to shut down the device; when the jumper is present the device is in SHUTDOWN
mode, to run the device remove the jumper. The other jumper, near the VREF test point, is used to set the PFM/
PSK mode. When the jumper is present, at light load, the system will go in PFM mode; if there is not the jumper,
at light load, the system will remain in PWM mode. In the demo bottom side there are two others different jump-
ers. They are used to set or remove the INTEGRATOR configuration. When the jumpers named with INT label
are closed AND the jumpers named with the NOINT label are open the integrator configuration is set. Some-
times the integrator configuration needs a low frequency filter the to reduce the noise interaction. In this case
instead close the INT jumpers put there a resistor and after a capacitor to ground (as in the schematic diagram);
the pole value is around 500Khz but it should be higher enough than the switching frequency (ten times). On
the opposite when the jumpers named with the NOINT are closed and the jumpers named with INT are open
the NON INTEGRATOR configuration is selected. Refer to the Table 1 and 2 for the jumpers connection.
Figure 10. Demoboard Schematic Diagram
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L6997
5.2 Jumper Connection
Table 6. Jumper connection with integrator
* This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 7. Jumper connection without integrator
5.3 DEMOBOARD LAYOUT
Real dimensions: 4,7 cm X 2,7 cm (1.85 inch X 1. 063 inch)
Figure 11. Top side components placement
Figure 12. Bottom side Jumpers distribution
Figure 13. Top side layout
Figure 14. Bottom side layout
L6997
Table 8. PCB Layout guidelines
Table 9. Component list
The component list is shared in two sections: the first for the general-purpose component, the second for
power section:
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Notes:1. N.M.=Not Mounted The demoboard with this component list is set to give: VOUT = 1.25V, FSW = 270kHz with an input voltage around VIN = VCC =
3.3V-5V and with the integrator feature. The diode efficiency impact is very low; it is not a necessary component. All capacitors are intended ceramic type otherwise specified.
5.4 EFFICIENCY CURVES
Source mode
VIN = 3.3V VOUT = 1.25V FSW = 270kHz
Figure 15. Efficiency vs output current
Table 9. Component list (continued)
The component list is shared in two sections: the first for the general-purpose component, the second for
power section:

Partno	Mfg	Dc	Qty	Available	Descript
L6997	ST	N/a	73	avai	STEP DOWN CONTROLLER FOR LOW VOLTAGES OPERATIONS