L6995STR Fast Delivery |IC PHOENIX CO.,LIMITED

L6995STR ,STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSIONAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6996 ,DINAMICALLY PROGRAMMABLE SYNCHRONOUS STEP DOWN CONTROLLER FOR MOBILE CPUsABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6997 ,STEP DOWN CONTROLLER FOR LOW VOLTAGES OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L6997S ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSElectrical Characteristics (continued)(V = V = 3.3V; T = 0°C to 85°C unless otherwise specified)CC ..
L6997STR ,STEP DOWN CONTROLLER FOR LOW VOLTAGE OPERATIONSAbsolute Maximum RatingsSymbol Parameter Value UnitV V to GND -0.3 to 6 VCC CCV V to GND -0.3 to 6 ..
L702B ,2A QUAD DARLINGTON SWITCHL7022A QUAD DARLINGTON SWITCHSUSTAINING VOLTAGE: 70 V2 A OUTPUTHIGH CURRENT GAINIDEAL FOR DRIVING S ..
LC4128V-5T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5T144C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-5TN128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75T144I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128V-75TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs

L6995STR
STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION
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April 2004 FEATURES CONSTANT ON TIME TOPOLOGY ALLOWS
OPERATION WITH LOWER DUTY THAN
PWM TOPOLOGY VERY FAST LOAD TRANSIENTS 5V Vcc SUPPLY 1.5V TO 35V INPUT VOLTAGE RANGE 0.9V ±1% VREF MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V SELECTABLE SINKING MODE LOSSLESS CURRENT LIMIT REMOTE SENSING OVP,UVP LATCHED PROTECTIONS 600µA TYP QUIESCENT CURRENT POWER GOOD AND OVP SIGNALS PULSE SKIPPING AT LIGHT LOADS APPLICATIONS I/O BUS FOR CPU CORE SUPPLY NOTEBOOK COMPUTERS NETWORKING DC-DC DISTRIBUTED POWER DESCRIPTION
The device is a step-down controller specifically de-
signed to provide extremely high efficiency conver-
sion, with losses current sensing tecnique.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feed-for-
ward" provides nearly constant switching frequency
operation.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The available remote sensing improve the static and
dynamic regulation recovering the wires voltage
drop. Pulse skipping technique reduces power con-
sumption at light load. Drivers current capability al-
lows output current in excess of 20A.
STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL
INPUT-OUTPUT CONVERSION
Figure 2. Minimum Component Count Application
REV. 1
Figure 1. Package
Table 1. Order Codes
L6995S
Table 2. Absolute Maximum Ratings
Table 3. Thermal Data
Figure 3. Pin Connection (Top View)
Table 4. Pin Function
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Table 5. Electrical Characteristics
(VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified)
Table 4. Pin Function (continued)
L6995S
Table 5. Electrical Characteristics (continued)
(VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified)
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Figure 4. Functional & Block Diagram
L6995S DEVICE DESCRIPTION
4.1 Constant On Time PWM topology
Figure 5. Loop block schematic diagram
The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time
duration forced by the one-shot generator. The on time is directly proportional to VSENSE pin voltage and in-
verse to OSC pin voltage as in Eq1:
Eq 1
where KOSC = 250ns and τ is the internal propagation delay time (typ. 70ns). The system imposes in steady
state a minimum on time corresponding to VOSC = 2V. In fact if the VOSC voltage increases above 2V the cor-
responding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a
steady-state switching frequency FSW independent of VIN. It results:
Eq 2
where
Eq 3
Eq 4
The above equations allow setting the frequency divider ratio αOSC once output voltage has been set; note that
such equations hold only if VOSC<2V. Further the Eq2 shows how the system has a switching frequency ideally
independent from the input voltage. The delay introduces a light dependence from VIN. A minimum off-time con-
strain of about 580ns is introduced in order to assure the boot capacitor charge and to limit the switching fre-ON K OSC SENSE OSC -------------------- τ+=SW OUTIN
---------------1ON
----------- α OSC OUT
--------------- 1 OSC
--------------- α OSC→ fSWK OSCα OUT== = OSC OSCIN -------------- R22 R1+--------------------== OUTFB OUT
--------------- R43 R4+--------------------==
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quency after a load transient as well as to mask PWM comparator output against noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.
4.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage
(0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise
spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then
turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 3.
The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC
error. Further the system regulates the output voltage valley value not the average, as in the Figure 5 is shown.
So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate
the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to
the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 6. The internal integrator am-
plifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides an AC path
for output ripple.
Figure 6. Valley regulation
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage
ranges from VREF-50mV, VREF+150mV. This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case of the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose
CINT1 according to the following equation:
Eq 5
where GINT=50 µs is the integrator transconductance, αOUT is the output divider ratio given from Eq4 and FU
is the close loop bandwidth. This equation also holds if CINT2 is connected between INT pin and ground. CINT2
is given by: INT1 INTα OUT⋅πFu⋅⋅------- ------------------------=
L6995S
Eq 6
Where ΔVOUT is the output ripple and ΔVINT is the ripple wanted at the INT pin (100mV typ).
Figure 7. Integrator loop block diagram
Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hys-
teretic system the frequency can change with some parameters (input voltage, output current). In L6995S is im-
plemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate
operation with the input voltage variation. There are many factors affecting switching frequency accuracy in
steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver.
Others related to the external components as high side MOSFET gate charge and gate resistance, voltage
drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.
During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
4.3 Transition from PWM to PFM/PSK
To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turns-
on the low side MOSFET, until the inductor current reaches the zero A value, when the zero-crossing compar-
ator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground,
through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps
the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow
through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in
fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOS-
FET when the output voltage goes down a reference value. The device works in discontinuous mode at light
load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around
half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the in- INT2 INT1
---------------- V OUTΔ INT
------------------=
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ductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the
transient response is. In PFM mode the frequency changes, with the output current changing, more than in
PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive
turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and
asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM
is not compatible with the application it can be disabled connecting to VCC the NOSKIP pin.
4.4 Softstart
If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side
MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to in-
crease and the system starts to switch. The softstart is realized by gradually increasing the current limit thresh-
old to avoid output overvoltage. The active soft start range for the VSS voltage (where the output current limit
increase linearly) starts from 0.6V to 1.5V. In this range an internal current source (5µA Typ) charges the ca-
pacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM pin is propor-
tional to SS pin voltage and it saturates at 5µA (Typ.) when SS voltage is close to 1.5V and the maximum current
limit is active. Undervoltage protection is disabled until SS pin voltage reaches 1.5V; instead the overvoltage is
always present (see figure 7).
Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation
anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first
turn-on the power section and after the logic section (VCC pin).
Figure 8. Soft -Start Diagram
Because the system implements the soft start controlling the inductor current, the soft start capacitor selection
is function of the output capacitance, the current limit and the soft start active range (ΔVSS).
In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before
the soft start voltage reaches the under voltage value (1.5V). In other words the output voltage charging time
has to be lower than the uvp time.
The UVP time is given by:
Eq 7
In order to calculate the output volatge chargin time it should be calculated, before, the output volatrge function
versus time. This function can be calculated from the inductor current function; the inductor current function can uvpCSS() V uvp
Iss------------ CSS⋅=
L6995S
be supposed linear function of the time.
Eq 8
so the output voltage is given by:
Eq 9
calling Vout as the Vout final value, the output charging time can be estimated as:
Eq 10
the minimum CSS value is given imposing this condition:
Eq 11 Tout =Tuvp
4.5 Current limit
The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and com-
pares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the one-shot start.
To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, VIN VOUT and switching frequency.
The average output current in current limit is given by:
Eq 12
Thus, to set the current threshold, choose RILIM according to the following equation:
Eq 13
In current limit the system keeps the current constant until the output voltage meets the undervolatge threshold.
The system is capable to sink current, but it has not a negative current limit.
The system accuracy is function of the exactness of the resistance connected to ILIM pin and the low side MOS-
FET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the sys-
tem linearity.
Figure 9. Current limit schematicL t,CSS() R ilim/R dson KCISSt⋅⋅ ⋅()SSCSS⋅Δ ()-------------------------- ---------------- --------------- ----------=out t,CSS() Qt,CSS()out
------------------------- R ilim/R dson KCISSt2⋅⋅ ⋅()out VSS CSS2⋅⋅Δ⋅ ()-------- --------------- ---------------- --------------- ----------------==outCSS() VoutCout VSS CSS2⋅⋅Δ⋅⋅ ilim/R dsonKCISS⋅⋅ ()-------------------------------------- ---------------- ----------
0.5 OUTCL I max valley IΔ-----+= max valley ILim
Rdson
----- ------------I Lim
5.2----------⋅=
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4.6 Protection and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of
the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low
side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects
an overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply
has to be removed, and restart with the correct sequence.
These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV
fault).
4.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran-
sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt-
age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOS-
FETS.
The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the ex-
ternal power MOSFET gate charge and switching frequency.
Eq 14
The maximum gate charge values for the low side and high side are given from:
Eq 15
Eq 16
Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is QMAXLS = 125nC.
The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect. APPLICATION INFORMATION
5.1 20A Demo board description
The demoboard shows the device operation in general purpose applications. The evaluation board allows using
only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device
through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1
is used to start the device (when the supplies are already present) and to select the PFM/PWM mode. driver Vcc Q gTOTFSW⋅⋅= MAXHS SW0SW
------------- 75nC⋅= MAXLS SW0SW
------------- 125nC⋅=
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Figure 10. Demoboard Schematic Diagram
5.2 Jumper Connection
Table 6. Jumper connection with integrator
* This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 7. Jumper connection without integrator
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5.3 NOTE
There is a linear regulator on board, it allows to use one generator (only for the power section, in fact the IC
section is powered by the linear regulator); if the regulator is used close the J1, other wise it has to keep open.
Be careful measuring the efficiency with the linear regulator asserted.
At high current in the integrator configuration (around 20A), it can be seen an oscillation in the switching fre-
quency due to the noise interaction, to reduce this oscillation put a noise filter RN, CN like in the figure 9. Note
the RN resistor is in the place of the INT jumper near C4. RN, CN, should be selected with a pole frequency
around 1Mhz, but anyway higher than switching frequency (five times).
5.4 DEMOBOARD LAYOUT
Real dimensions: 5,7 cm X 7,7 cm (2,28inch X 3, 08inch)
Figure 11. PCB layout: bottom side
Figure 12. PCB Layout: Top side
Figure 13. Internal ground plane
Figure 14. Power & signal plane

Partno	Mfg	Dc	Qty	Available	Descript
L6995STR	ST	N/a	10000	avai	STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL INPUT-OUTPUT CONVERSION