L6919CD ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENTBLOCK DIAGRAMO OS SC C / / IIN NH H SG SGND ND V VC CCD CDR RBO BOO O T T1 1HS HSU UP PGOO GOOD D G ..
L6919E ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENTBLOCK DIAGRAMOS OSC C / / IIN NH H S SG GN N D D V VCCD CCD R RBO BO O O T T 1 1HS HSP PG GOOD OOD ..
L6919ETR ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENTL6919E5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLERWITH DYNAMIC VID MANAGEMENT■ 2 PHASE OPERATION WITH S ..
L6920 ,1V HIGH EFFICIENCY SYNCHRONOUS STEP UP CONVERTERApplicationsThe L6920 is a high efficiency step-up controller re-■ ONE TO THREE CELL BATTERY DEVICE ..
L6920D ,1V HIGH EFFICIENCY SYNCHRONOUS STEP UP CONVERTERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV V to GND 6 Vccmax ccLBI, SHDN, FB to GND 6 VV ..
L6920DB ,Synchronous rectifier step up converterfeatures■ 0.8V start up input voltage■ Up to 5.5V operating input voltage■ Internal synchronous rec ..
LC4128B-10TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128B-75T128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128B-75TN100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6919CD
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENT
1/32
L6919CDecember 2002 2 PHASE OPERATION WITH
SYNCRHONOUS RECTIFIER CONTROL ULTRA FAST LOAD TRANSIENT RESPONSE INTEGRATED HIGH CURRENT GATE
DRIVERS: UP TO 2A GATE CURRENT TTL-COMPATIBLE 5 BIT PROGRAMMABLE OUTPUT FROM 0.800V TO 1.550V WITH
25mV STEPS DYNAMIC VID MANAGEMENT 0.6% OUTPUT VOLTAGE ACCURACY 10% ACTIVE CURRENT SHARING ACCURACY DIGITAL 2048 STEP SOFT-START OVERVOLTAGE PROTECTION OVERCURRENT PROTECTION REALIZED
USING THE LOWER MOSFET'S RdsON OR A
SENSE RESISTOR OSCILLATOR EXTERNALLY ADJUSTABLE
AND INTERNALLY FIXED AT 200kHz POWER GOOD OUTPUT AND INHIBIT
FUNCTION REMOTE SENSE BUFFER PACKAGE: SO-28
APPLICATIONS POWER SUPPLY FOR SERVERS AND
WORKSTATIONS POWER SUPPLY FOR HIGH CURRENT
MICROPROCESSORS DISTRIBUTED POWER SUPPLY
DESCRIPTIONThe device is a power supply controller specifically de-
signed to provide a high performance DC/DC conver-
sion for high current microprocessors. The device
implements a dual-phase step-down controller with a
180° phase-shift between each phase. A precise 5-bit
digital to analog converter (DAC) allows adjusting the
output voltage from 0.800V to 1.550V with 25mV binary
steps managing On-The-Fly VID code changes.
The high precision internal reference assures the se-
lected output voltage to be within ±0.6%. The high
peak current gate drive affords to have fast switching
to the external power mos providing low switching
losses.
The device assures a fast protection against load
over current and load over/under voltage. An internal
crowbar is provided turning on the low side mosfet if
an over-voltage is detected. In case of over-current,
the system works in Constant Current mode.
5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER
WITH DYNAMIC VID MANAGEMENT
BLOCK DIAGRAM
L6919C2/32
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
PIN CONNECTION
3/32
L6919C
ELECTRICAL CHARACTERISTICS VCC = 12V ±10%, TJ = 0 to 70°C unless otherwise specified
L6919C4/32
ELECTRICAL CHARACTERISTICS (continued)VCC = 12V ±10%, TJ = 0 to 70°C unless otherwise specified
5/32
L6919C
Table 1. Voltage Identification (VID) Codes
Reference Schematic
L6919C6/32
PIN FUNCTION
7/32
L6919C
PIN FUNCTION (continued)
L6919C8/32
DEVICE DESCRIPTIONThe device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance dual-phase step-down DC-DC converter optimized for microprocessor power supply. It
is designed to drive N Channel MOSFETs in a dual-phase synchronous-rectified buck topology. A 180 deg
phase shift is provided between the two phases allowing reduction in the input capacitor current ripple, reducing
also the size and the losses. The output voltage of the converter can be precisely regulated, programming the
VID pins, from 0.800V to 1.550V with 25mV binary steps, with a maximum tolerance of ±0.6% over temperature
and line voltage variations. The device manages On-The-Fly VID Code changes stepping to the new configu-
ration following the VID table with no need for external components. The device provides an average current-
mode control with fast transient response. It includes a 200kHz free-running oscillator. The error amplifier fea-
tures a 15V/μs slew rate that permits high converter bandwidth for fast transient performances. Current infor-
mation is read across the lower mosfets RdsON or across a sense resistor in fully differential mode. The current
information corrects the PWM output in order to equalize the average current carried by each phase. Current
sharing between the two phases is then limited at ±10% over static and dynamic conditions. The device protects
against Over-Current, with an OC threshold for each phase, entering in constant current mode. Since the current
is read across the low side mosfets, the constant current keeps constant the bottom of the inductors current
triangular waveform. When an under voltage is detected the device latches and the FAULT pin is driven high.
The device performs also Over-Voltage protection that disables immediately the device turning ON the lower
driver and driving high the FAULT pin.
OSCILLATORThe switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the
PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is
typically 17μA (Fsw=200KHz) and may be varied using an external resistor (ROSC) connected between OSC pin and
GND or Vcc. Since the OSC pin is maintained at fixed voltage (Typ. 1.235V), the frequency is varied proportionally to
the current sunk (forced) from (into) the pin considering the internal gain of 12KHz/μA.
In particular connecting it to GND the frequency is increased (current is sunk from the pin), while connecting ROSC
to Vcc=12V the frequency is reduced (current is forced into the pin), according to the following relationships:
Note that forcing a 17μA current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1. ROSC vs. Switching Frequency OSC vs. GND: fS 200kHz 1.237 OSC KΩ()--------------- --------------- 12 kHz-----------⋅+ 200kHz 14.82 106⋅ OSC KΩ()----- -------------------------+== OSC vs. 12V: fS 200kHz 12 1.237– OSC KΩ()------------------------------ 12 kHz-----------⋅– 200kHz 12.918 107⋅ OSC KΩ()--------- -----------------------–==
9/32
L6919C
DIGITAL TO ANALOG CONVERTERThe built-in digital to analog converter allows the adjustment of the output voltage from 0.800V to 1.550V with
25mV as shown in the previous table 1. The internal reference is trimmed to ensure output voltage precision of
±0.6% and a zero temperature coefficient around 70°C. The internal reference voltage for the regulation is pro-
grammed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is
realized by means of a series of resistors providing a partition of the internal voltage reference. The VID code
drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an
amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are
provided (realized with a 5μA current generator up to 3.3V Typ); in this way, to program a logic "1" it is enough
to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. Programming the
"11111" code, the device enters the NOCPU mode: all mosfets are turned OFF and protections are diabled. The
condition is latched.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the Over
/ Under Voltage protection (OVP/UVP) thresholds.
DYNAMIC VID TRANSITIONThe device is able to manage On-The-Fly VID Code changes that allow Output Voltage modification during nor-
mal device operation. The device checks every clock cycle (synchronously with the PWM ramp) for VID code
modifications. Once the new code is stable for more than one clock cycle, the reference steps up or down in
25mV increments every clock cycle until the new VID code is reached. During the transition, VID code changes
are ignored; the device re-starts monitoring VID after the transition has finished. PGOOD, signal is masked dur-
ing the transition and it is re-activated after the transition has finished while OVP / UVP are still active.
Figure 2. Dynamic VID transition
SOFT START AND INHIBITAt start-up a ramp is generated increasing the loop reference from 0V to the final value programmed by VID in
2048 clock periods as shown in figure 3.
Before soft start, the lower power MOS are turned ON after that VCCDR reaches 2V (independently by Vcc val-
ue) to discharge the output capacitor and to protect the load from high side mosfet failures. Once soft start be-
gins, the reference is increased; also the upper MOS begins to switch and the output voltage starts to increase
with closed loop regulation. At the end of the digital soft start, the Power Good comparator is enabled and the
PGOOD signal is then driven high (See fig. 3). The Under Voltage comparator enabled when the reference volt-
age reaches 0.8V. The Soft-Start will not take place, if both VCC and VCCDR pins are not above their own turn-
on thresholds. During normal operation, if any under-voltage is detected on one of the two supplies the device
shuts down. Forcing the OSC/INH/FAULT pin to a voltage lower than 0.6V (Typ.), the device enters in INHIBIT
mode: all the power mosfets are turned off and protections are disabled.
Setting the INH pin free, causes the device to restart.
L6919C10/32
Figure 3. Soft Start
Figure 4. Drivers peak current: High Side (left) and Low Side (right)
DRIVER SECTIONThe integrated high-current drivers allow using different types of power MOS (also multiple MOS to reduce the
RdsON), maintaining fast switching transition.
The drivers for the high-side mosfets use BOOTx pins for supply and PHASEx pins for return. The drivers for
the low-side mosfets use VCCDRV pin for supply and PGND pin for return. A minimum voltage of 4.6V at VC-
CDRV pin is required to start operations of the device.
The controller embodies a sophisticated anti-shoot-through system to minimize low side body diode conduction
time maintaining good efficiency saving the use of Schottky diodes. The dead time is reduced to few nanosec-
onds assuring that high-side and low-side mosfets are never switched on simultaneously: when the high-side
mosfet turns off, the voltage on its source begins to fall; when the voltage reaches 2V, the low-side mosfet gate
drive is applied with 30ns delay. When the low-side mosfet turns off, the voltage at LGATEx pin is sensed. When
it drops below 1V, the high-side mosfet gate drive is applied with a delay of 30ns. If the current flowing in the
inductor is negative, the source of high-side mosfet will never drop. To allow the turning on of the low-side mos-
fet even in this case, a watchdog controller is enabled: if the source of the high-side mosfet don't drop for more
than 240ns, the low side mosfet is switched on so allowing the negative current of the inductor to recirculate.
This mechanism allows the system to regulate even if the current is negative.
11/32
L6919CThe BOOTx and VCCDR pins are separated from IC's power supply (VCC pin) as well as signal ground (SGND
pin) and power ground (PGND pin) in order to maximize the switching noise immunity. The separated supply
for the different drivers gives high flexibility in mosfet choice, allowing the use of logic-level mosfet. Several com-
bination of supply can be chosen to optimize performance and efficiency of the application. Power conversion
is also flexible; 5V or 12V bus can be chosen freely.
The peak current is shown for both the upper and the lower driver of the two phases in figure 3. A 10nF capac-
itive load has been used. For the upper drivers, the source current is 1.9A while the sink current is 1.5A with
VBOOT -VPHASE = 12V; similarly, for the lower drivers, the source current is 2.4A while the sink current is 2A with
VCCDR = 12V.
CURRENT READING AND OVER CURRENTThe current flowing trough each phase is read using the voltage drop across the low side mosfets RdsON or
across a sense resistor (RSENSE) and internally converted into a current. The Tran conductance ratio is issued
by the external resistor Rg placed outside the chip between ISENx and PGNDSx pins toward the reading points.
The full differential current reading rejects noise and allows to place sensing element in different locations with-
out affecting the measurement's accuracy. The current reading circuitry reads the current during the time in
which the low-side mosfet is on (OFF Time). During this time, the reaction keeps the pin ISENx and PGNDSx
at the same voltage while during the time in which the reading circuitry is off, an internal clamp keeps these two
pins at the same voltage sinking from the ISENx pin the necessary current (Needed if low-side mosfet RdsON
sense is implemented to avoid absolute maximum rating overcome on ISENx pin).
The proprietary current reading circuit allows a very precise and high bandwidth reading for both positive and
negative current. This circuit reproduces the current flowing through the sensing element using a high speed
Track & Hold Tran conductance amplifier. In particular, it reads the current during the second half of the OFF
time reducing noise injection into the device due to the mosfet turn-on (See fig. 5). Track time must be at least
200ns to make proper reading of the delivered current
Figure 5. Current Reading Timing (Left) and Circuit (Right)This circuit sources a constant 50μA current from the PGNDSx pin and keeps the pins ISENx and PGNDSx at
the same voltage. Referring to figure 4, the current that flows in the ISENx pin is then given by the following
equation:
Where RSENSE is an external sense resistor or the rds,on of the low side mosfet and Rg is the transconductance
resistor used between ISENx and PGNDSx pins toward the reading points; IPHASE is the current carried by each
phase and, in particular, the current measured in the middle of the oscillator period
The current information reproduced internally is represented by the second term of the previous equation as ISENx 50μA R SENSEI PHASE⋅g
-------- ---------------- ----------------------+ 50μAI INFOx+==
L6919C12/32
follow:
Since the current is read in differential mode, also negative current information is kept; this allow the device to
check for dangerous returning current between the two phases assuring the complete equalization between the
phase's currents. From the current information of each phase, information about the total current delivered (IFB
=IINFO1 +IINFO2) and the average current for each phase (IAVG =(IINFO1 +IINFO2)/2 ) is taken. IINFOX is then com-
pared to IAVG to give the correction to the PWM output in order to equalize the current carried by the two phases.
The transconductance resistor Rg can be designed in order to have current information of 25μA per phase at
full nominal load; the over current intervention threshold is set at 140% of the nominal (IINFOx = 35μA). According
to the above relationship, the over current threshold (IOCPx) for each phase, which has to be placed at one half
of the total delivered maximum current, results:
Since the device senses the output current across the low-side mosfets (or across a sense resistors in series
with them) the device limits the bottom of the inductor current triangular waveform: an over current is detected
when the current flowing into the sense element is greater than IOCPx (IINFOx > 35μA).
Introducing now the maximum ON time dependence with the delivered current (where T is the switching period
T=1/fSW):
This linear dependence has a value at zero load of 0.80·T and at maximum current of 0.40·T typical and results
in two different behaviors of the device:
1. TON Limited Output Voltage. This happens when the maximum ON time is reached before the current in each phase reaches IOCPx (IINFOx
< 35μA).
Figure 6a shows the maximum output voltage that the device is able to regulate considering the TON limitation
imposed by the previous relationship. If the desired output characteristic crosses the TON limited maximum output
voltage, the output resulting voltage will start to drop after crossing. In this case, the device doesn't perform con-
stant current limitation but only limits the maximum ON time following the previous relationship. The output volt-
age follows the resulting characteristic (dotted in Figure 6b) until UVP is detected or anyway until IFB = 70μA.
Figure 6. TON Limited Operation INFOx SENSEI PHASE⋅g
--------- --------------- ----------------------= OCPx
35μARg⋅ SENSE
-------- -------------------= Rg I OCPxR SENSE⋅
35μA----------------------------- --------------= ON,MAX 0.80 IFB 5.73k⋅ ()T⋅– 0.80 R SENSE----------------------I OUT 5.73k⋅⋅ T
0.80 T IFB⋅ 0μA =
0.40 T IFB⋅ 70μA=⋅–==
13/32
L6919C
2. Constant Current OperationThis happens when ON time limitation is reached after the current in each phase reaches IOCPx (IINFOx>35μA).
The device enters in Quasi-Constant-Current operation: the low-side mosfets stays ON until the current read
becomes lower than IOCPx (IINFOx < 35μA) skipping clock cycles. The high side mosfets can be turned ON with
a TON imposed by the control loop at the next available clock cycle and the device works in the usual way until
another OCP event is detected.
This means that the average current delivered can slightly increase also in Over Current condition since the cur-
rent ripple increases. In fact, the ON time increases due to the OFF time rise because of the current has to reach
the IOCPx bottom. The worst-case condition is when the ON time reaches its maximum value.
When this happens, the device works in Constant Current and the output voltage decrease as the load increase.
Crossing the UVP threshold causes the device to latch (FAULT pin is driven high).
Figure 7 shows this working condition
Figure 7. Constant Current operationIt can be observed that the peak current (Ipeak) is greater than the IOCPx but it can be determined as follow:
Where VoutMIN is the minimum output voltage (VID-30% as follow).
The device works in Constant-Current, and the output voltage decreases as the load increase, until the output
voltage reaches the Under-Voltage threshold (VoutMIN). When this threshold is crossed, all mosfets are turned
off, the FAULT pin is driven high and the device stops working. Cycle the power supply to restart operation. The
maximum average current during the Constant-Current behavior results:
In this particular situation, the switching frequency results reduced. The ON time is the maximum allowed
(TonMAX) while the OFF time depends on the application:
Over current is set anyway when IINFOx reaches 35μA (IFB = 70μA). The full load value is only a convention
to work with convenient values for IFB. Since the OCP intervention threshold is fixed, to modify the percent-
age with respect to the load value, it can be simply considered that, for example, to have on OCP threshold
of 170%, this will correspond to IINFOx = 35μA (IFB = 70μA). The full load current will then correspond to
IINFOx = 20.6μA (IFB = 41.1μA).
Ipeak I OCPxIN Vout MIN–-------- --------------- ---------------- Ton MAX⋅+ I OCPxIN Vout MIN–------- --------------- ----------------- 0.40T⋅⋅+== MAX,TOT 2I MAX 2I OCPx
IpeakI OCPx–-------- --------------- ---------------+ ⋅+⋅= OFF L IpeakI OCPx– OUT
---------- --------------- -------------⋅= f 1 ONmax T OFF+ ------------------------------------------=
L6919C14/32
Integrated Droop FunctionThe device uses a droop function to satisfy the requirements of high performance microprocessors, reducing
the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current
As shown in figure 8, the ESR drop is present in any case, but using the droop function the total deviation of the
output voltage is minimized. In practice the droop function introduces a static error (VDROOP in figure 8) propor-
tional to the output current. Since the device has an average current mode regulation, the information about the
total current delivered is used to implement the Droop Function. This current (equal to the sum of both IINFOx)
is sourced from the FB pin. Connecting a resistor between this pin and VOUT, the total current information flows
only in this resistor because the compensation network between FB and COMP has always a capacitor in series
(See fig. 9). The voltage regulated is then equal to:
VOUT = VID - RFB · IFB
Since IFB depends on the current information about the two phases, the output characteristic vs. load current is
given by:
Figure 8. Output transient response without (a) and with (b) the droop function
Figure 9. Active Droop Function CircuitThe feedback current is equal to 50μA at nominal full load (IFB = IINFO1 + IINFO2) and 70μA at the OC intervention
threshold, so the maximum output voltage deviation is equal to:
ΔVFULL_POSITIVE_LOAD = -RFB · 50μA ΔVOC_INTERVENTION = -RFB · 70μA
Droop function is provided only for positive load; if negative load is applied, and then IINFOx < 0, no current is
sunk from the FB pin. The device regulates at the voltage programmed by the VID. OUT VID RFB SENSE------- ---------------I OUT⋅⋅–=
15/32
L6919C
OUTPUT VOLTAGE MONITOR AND PROTECTIONSThe output voltage is monitored by pin VSEN. If it is not within ±12% (Typ.) of the programmed value, the power
good output is forced low. Power good is an open drain output and it is enabled only after the soft start is finished
(2048 clock cycles after start-up).
The device provides over voltage protection; when the voltage sensed by the VSEN pin reaches 1.976V (typ.),
the controller permanently switches on both the low-side mosfets and switches off both the high-side mosfets
in order to protect the CPU. The OSC/INH/FAULT pin is driven high (5V) and power supply (Vcc) turn off and
on is required to restart operations. The over Voltage percentage is set by the ratio between the OVP threshold
(set at 1.976V) and the reference programmed by VID.
Under voltage protection is also provided. If the output voltage drops below the 70% of the reference voltage for
more than one clock period the device turns off and the FAULT is driven high.
Both Over Voltage and Under Voltage are active also during soft start (Under Voltage after than VOUT reaches
0.8V). During soft-start the reference voltage used to determine the UV threshold is the increasing voltage driv-
en by the 2048 soft start digital counter.
REMOTE VOLTAGE SENSEA remote sense buffer is integrated into the device to allow output voltage remote sense implementation without
any additional external components. In this way, the output voltage programmed is regulated between the re-
mote buffer inputs compensating motherboard trace losses or connector losses if the device is used for a VRM
module. The very low offset amplifier senses the output voltage remotely through the pins FBR and FBG (FBR
is for the regulated voltage sense while FBG is for the ground sense) and reports this voltage internally at VSEN
pin with unity gain eliminating the errors.
If remote sense is not required, the output voltage is sensed by the VSEN pin connecting it directly to the output
voltage. In this case the FBG and FBR pins must be connected anyway to the regulated voltage.
INPUT CAPACITORThe input capacitor is designed considering mainly the input RMS current that depends on the duty cycle as
reported in figure 10. Considering the dual-phase topology, the input RMS current is highly reduced comparing
with a single phase operation.
Figure 10. Input RMS Current vs. Duty Cycle (D) and Driving RelationshipsOVP%[] 1.976V
ReferenceVoltage VID()----------- --------------- --------------- --------------- --------------- 100⋅=
L6919C16/32
It can be observed that the input rms value is one half of the single-phase equivalent input current in the worst
case condition that happens for D = 0.25 and D = 0.75.
The power dissipated by the input capacitance is then equal to:
Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the
high RMS value needed by the CPU power supply application and also to minimize components cost, the input
capacitance is realized by more than one physical capacitor. The equivalent RMS current is simply the sum of
the single capacitor's RMS current.
Input bulk capacitor must be equally divided between high-side drain mosfets and placed as close as possible
to reduce switching noise above all during load transient. Ceramic capacitor can also introduce benefits in high
frequency noise decoupling, noise generated by parasitic components along power path.
OUTPUT CAPACITORSince the microprocessors require a current variation beyond 50A doing load transients, with a slope in the
range of tenth A/μs, the output capacitor is a basic component for the fast response of the power supply.
Dual phase topology reduces the amount of output capacitance needed because of faster load transient response
(switching frequency is doubled at the load connections). Current ripple cancellation due to the 180° phase shift
between the two phases also reduces requirements on the output ESR to sustain a specified voltage ripple.
When a load transient is applied to the converter's output, for first few microseconds the current to the load is
supplied by the output capacitors. The controller recognizes immediately the load transient and increases the
duty cycle, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
ΔVOUT = ΔIOUT · ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where DMAX is the maximum duty cycle value. The lower is the ESR, the lower is the output drop during load
transient and the lower is the output voltage static ripple.
INDUCTOR DESIGNThe inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ΔIL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. The response time is the time required by the inductor to change its current
from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by
the output capacitors. Minimizing the response time can minimize the output capacitance required.
The response time to a load transient is different for the application or the removal of the load: if during the ap- RMS ESRI RMS()2⋅= OUTΔ I OUTΔ L⋅ OUT VIN D MAX V OUT–⋅ ()⋅⋅------------ ---------------- --------------- --------------- --------------- ----------= VIN V OUT–SW ILΔ⋅ ------------------------------V OUTIN
---------------⋅=
