L6911ETR ,5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATIONABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVcc Vcc to GND, PGND 15 VV -V Boot Voltage 15 VB ..
L6917 ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLERELECTRICAL CHARACTERISTICS V = 12V ±10%, T = 0 to 70°C unless otherwise specifiedCC JSymbol Paramet ..
L6917B ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLERELECTRICAL CHARACTERISTICS V = 12V ±10%, T = 0 to 70°C unless otherwise specifiedCC JSymbol Paramet ..
L6917BD ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLERL6917B5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER■ 2 PHASE OPERATION WITH SYNCRHONOUS RECTIFIER CONTRO ..
L6917BDTR ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLERELECTRICAL CHARACTERISTICS V = 12V ±10%, T = 0 to 70°C unless otherwise specifiedCC JSymbol Paramet ..
L6919CD ,5 BIT PROGRAMMABLE DUAL-PHASE CONTROLLER WITH DYNAMIC VID MANAGEMENTBLOCK DIAGRAMO OS SC C / / IIN NH H SG SGND ND V VC CCD CDR RBO BOO O T T1 1HS HSU UP PGOO GOOD D G ..
LC4128B-10TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128B-75T128C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128B-75TN100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4128C-75T100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6911E-L6911ETR
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER WITH SYNCHRONOUS RECTIFICATION
1/20
L6911ENovember 2001 OPERATING SUPPLY IC VOLTAGE FROM 5V
TO 12V BUSES UP TO 1.3A GATE CURRENT CAPABILITY TTL-COMPATIBLE 5 BIT PROGRAMMABLE
OUTPUT COMPLIANT WITH VRM 8.5 :
1.050V TO 1.825V WITH 0.025V BINARY
STEPS VOLTAGE MODE PWM CONTROL EXCELLENT OUTPUT ACCURACY: ±1%
OVER LINE AND TEMPERATURE
VARIATIONS VERY FAST LOAD TRANSIENT RESPONSE:
FROM 0% TO 100% DUTY CYCLE POWER GOOD OUTPUT VOLTAGE OVERVOLTAGE PROTECTION AND
MONITOR OVERCURRENT PROTECTION REALIZED
USING THE UPPER MOSFET'S RdsON 200KHz INTERNAL OSCILLATOR OSCILLATOR EXTERNALLY ADJUSTABLE
FROM 50KHz TO 1MHz SOFT START AND INHIBIT FUNCTIONS
APPLICATIONS POWER SUPPLY FOR ADVANCED
MICROPROCESSOR CORE DISTRIBUTED POWER SUPPLY
DESCRIPTIONThe device is a power supply controller specifically
designed to provide a high performance DC/DC con-
version for high current microprocessors. A precise 5
bit digital to analog converter (DAC) allows to adjust
the output voltage from 1.050 to 1.825 with 25mV bi-
nary steps.
The high precision internal reference assures the se-
lected output voltage to be within ±1%. The high peak
current gate drive affords to have fast switching to the
external power mos providing low switching losses.
The device assures a fast protection against load
overcurrent and load over-voltage. An external SCR
is triggered to crowbar the input supply in case of
hard overvoltage. An internal crowbar is also provid-
ed turning on the low side mosfet as long as the over-
voltage is detected. In case of over-current detection,
the soft start capacitor is discharged an the system
works in HICCUP mode.
5 BIT PROGRAMMABLE STEP DOWN CONTROLLER
WITH SYNCHRONOUS RECTIFICATION
BLOCK DIAGRAM
L6911E 2/20
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
3/20
L6911E
PIN FUNCTION
L6911E 4/20
ELECTRICAL CHARACTERISTIC (Vcc=12V; T=25°C unless otherwise specified)
5/20
L6911E
Table 1. VID Setting
Device DescriptionThe device is an integrated circuit realized in BCD technology. It provides complete control logic and protections
for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed
to drive N Channel Mosfets in a synchronous-rectified buck topology. The device works properly with Vcc rang-
ing from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The
output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V
with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The
device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator
that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/
ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty
cycle ranges from 0% to 100%. The device protects against over-current conditions entering in HICCUP mode.
The device monitors the current by using the rDS(ON) of the upper MOSFET which eliminates the need for a cur-
rent sensing resistor.
The device is available in SO20 package.
OscillatorThe switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform
for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the
oscillator is tipically 50μA (Fsw=200KHz) and may be varied using an external resistor (RT) connected between
RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied
proportionally to the current sinked (forced) from (into) the pin.
In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the
following relationship:
Connecting RT to VCC=12V or to VCC=5V the frequency is reduced (current is forced into the pin), according
to the following relationships:S 200kHz 4.94 106⋅T kΩ()---- ---------------------+=
L6911E 6/20
VCC = 12V
VCC = 5V
Switching frequency variations vs. RT are reported in Fig.1.
Note that forcing a 50μA current into this pin, the device stops switching because no current is delivered to the
oscillator.
Figure 1.
Digital to Analog ConverterThe built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with
25mV binary steps as shown in the previous table 1. The internal reference is trimmed to ensure the precision
of 1%.
The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These
are TTL compatible inputs of an internal DAC that is realised by means of a series of resistors rpoviding a par-
tition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise
point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the
set-point of the error amplifier). Internal pull-ups are provided (realized with a 5μA current generator); in this
way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short
the pin to GND.
The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over-
voltage protection (OVP) thresholds.
Soft Start and InhibitAt start-up a ramp is generated charging the external capacitor CSS by means of a 10μA constant current, as
shown in figure 2.
When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to dis-
charge the output capacitor. As VSS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upperS 200kHz 4.306 107⋅T kΩ()---- -------------------------+=S 200kHz 15 107⋅T kΩ()---- ----------------+=
7/20
L6911EMOS begins to switch and the output voltage starts to increase.
The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly in-
creases, as shown in figure 2. In this phase the system works in open loop. When VSS is equal to VCOMP the
clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of
the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage,
see figure 2). In this second phase the system works in closed loop with a growing reference. As the output
voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft
start finishes. Vss increases until a maximum value of about 4V.
The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins
are not above their own Turn-On thresholds; in this way the device starts switching only if both the power sup-
plies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS
pin is internally shorted to GND and so the SS capacitor is rapidly discharged.
The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept
off.
Figure 2. Soft Start
Driver SectionThe driver capability on the high and low side drivers allows to use different types of power MOS (also multiple
MOS to reduce the RDSON), maintaining fast switching transition.
The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin.
Adaptative dead time control is implemented to prevent cross-conduction and allow to use many kinds of mos-
fets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is
avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the
low side turn-off.
The peak current is shown for both the upper (fig. 3) and the lowr (fig. 4) driver at 5V and 12V. a 4nF capacitive
load has been used in these measurements.
For the lower driver, the source peak current is 1.1A @ Vcc=12V and 500mA @ Vcc=5V, and the sink peak
current is 1.3A @ Vcc=12V and 500mA @ Vcc=5V.
Similary, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase=12V and 600mA @ Vboot-
Vphase =5V, and the sink peak current is 1.3A @ Vboot-Vphase =12V and 550mA @ Vboot-Vphase =5V.
L6911E 8/20
Figure 3. High Side driver peak current.
Vboot-Vphase=12V (left) Vboot-Vphase=5V (right) CH1 = High Side Gate CH4 = Inductor Current
Figure 4. Low Side driver peak current.
Vcc=12V (left) Vcc=5V (right)CH1 = Low Side Gate CH4 = Inductor Current
Monitor and ProtectionThe output voltage is monitored by means of pin 1 (VSEN). If it is not within ±10% (typ.) of the programmed
value, the powergood output is forced low.
The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than
the nominal one. If the output voltage exceed this threshold, the OVP pin is forced high (5V) and the lower driver
is turned on as long as the over-voltage is detected. The OVP pin is capable to deliver up to 60mA (min) in order
to trigger an external SCR connected to burn the input fuse. The low-side mosfet turn-on implement this function
when the SCR is not used and helps in keeping the ouput low.
To perform the overcurrent protection the device compares the drop across the high side MOS, due to its
RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of
the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship:
where the typical value of IOCS is 200μA.
To calculate the ROCS value it must be considered the maximum RDSON (also the variation with temperature)
and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be
satisfied:P OCSR OCS⋅ DSON
--------------------------------=
9/20
L6911Ewhere ΔI is the inductance ripple current and IOUTMAX is the maximum output current.
In case of output short circuit the soft start capacitor is discharged with constant current (10μA typ.) and when
the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is al-
ways active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is di-
charged again after reaching the upper threshold of about 4V. The system is now working in HICCUP mode, as
shown in figure 5a. After removing the cause of the over-current, the device restart working normally without
power supplies turn off and on.
Figure 5.
Inductor designThe inductance value is defined by a compromise between the transient response time, the efficiency, the cost
and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain
the ripple current ΔIL between 20% and 30% of the maximum output current. The inductance value can be cal-
culated with this relationship:
Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 5b shows
the ripple current vs. the output voltage for different values of the inductor, with vin=5V and Vin=12V.
Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter
response time to a load transient. If the compensation network is well designed, the device is able to open or
close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to
change its current from initial to final value. Since the inductor has not finished its charging time, the output cur-
rent is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance
required.
The response time to a load transient is different for the application or the removal of the load: if during the ap-
plication of the load the inductor is charged by a voltage equal to the difference between the input and the output
voltage, during the removal it is discharged only by the output voltage. The following expressions give approx-
imate response time for ΔI load transient in case of enough fast compensation network response:PI OUTMAX-----+≥ I PEAK=IN V OUT–s ILΔ⋅ ------------------------------V OUTIN
--------------⋅=
L6911E 10/20
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst
case is the response time after removal of the load with the minimum output voltage programmed and the max-
imum input voltage available.
Output CapacitorSince the microprocessors require a current variation beyond 10A doing load transients, with a slope in the
range of tenth A/μsec, the output capacitor is a basic component for the fast response of the power supply. In
fact for first few microseconds they supply the current to the load. The controller recognizes immediately the
load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.
The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the
ESL):
ΔVOUT = ΔIOUT · ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The
voltage drop due to the output capacitor discharge is given by the following equation:
Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop
during load transient and the lower is the output voltage static ripple.
Input CapacitorThe input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must
have a low ESR to minimize the losses. The rms value of this ripple is:
Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:
Compensation network designThe control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM
module, reducing the size and the cost of the output capacitor.
This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-
pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-
inal level, while at high load the output voltage will be lower than the nominal value. application L ΔI⋅IN V OUT–- ---------------- -------------= t removal L ΔI⋅ OUT
----- ----------= OUT OUT L OUT V INMIN D MAX V OUT–⋅ ()⋅⋅---------------- --------------- --------------- --------------- --------------- -----------------= rms I OUT= ESRI rms⋅=
