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L6743Q-L6743QTR
High current MOSFET driver
June 2008 Rev 2 1/17
L6743
L6743QHigh current MOSFET driver
Features Dual MOSFET driver for synchronous rectified
converters High driving current for fast external MOSFET
switching Integrated bootstrap diode High frequency operation Enable pin Adaptive dead-time management Flexible gate-drive: 5 V to 12 V compatible High-impedance (HiZ) management for output
stage shutdown Preliminary OV protection SO-8 and DFN10 3x3 packages
Applications High current VRM / VRD for desktop / server /
workstation CPUs High current and high efficiency DC / DC
converters
DescriptionL6743, L6743Q is a flexible, high-frequency dual-
driver specifically designed to drive N-channel
MOSFETs connected in synchronous-rectified
buck topology.
Combined with ST PWM controllers, the driver
allows implementing complete voltage regulator
solutions for modern high-current CPUs and
DCDC conversion in general. L6743, L6743Q
embeds high-current drivers for both high-side
and low-side MOSFETS. The device accepts
flexible power supply (5 V to 12 V) to optimize the
gate-drive voltage for High-Side and Low-Side
maximizing the System Efficiency.
The Bootstrap diode is embedded saving the use
of external diodes. Anti shoot-through
management avoids high-side and low-side
MOSFET to conduct simultaneously and,
combined with Adaptive Dead-Time control,
minimizes the LS body diode conduction time.
L6743, L6743Q embeds Preliminary OV
Protection: after Vcc overcomes the UVLO and
while the device is in HiZ, the LS MOSFET is
turned ON to protect the load in case the output
voltage overcomes a warning threshold protecting
the output against HS failures.
The driver is available is SO-8 and DFN10 3x3
packages
Table 1. Device summary
Contents L6743, L6743Q2/17
Contents Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 31.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 42.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.1 High-impedance (HiZ) management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2 Preliminary OV protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.3 Internal BOOT diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.5 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
L6743, L6743Q Typical application circuit and block diagram
3/17 Typical application circuit and block diagram
1.1 Application circuit
Figure 1. Typical application circuit
1.2 Block diagram
Figure 2. Block diagram
Pin description and connection diagrams L6743, L6743Q
4/17 Pin description and connection diagrams
Figure 3. Pin connection (top view)
2.1 Pin description
Table 2. Pin description
L6743, L6743Q Thermal data
5/17
3 Thermal data
Table 3. Thermal data
4 Electrical specifications
4.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
Electrical specifications L6743, L6743Q
6/17
4.2 Electrical characteristics
Table 5. Electrical characteristics
(VCC = 12 V±15 %, TJ = 0 °C to 70 °C unless otherwise specified). Parameter(s) guaranteed by designed, not fully tested in production
L6743, L6743Q Device description and operation
7/17 Device description and operation
L6743, L6743Q provides high-current driving control for both high-side and low-side
N-channel MOSFETS connected as step-down DC-DC Converter driven by an external
PWM signal. The integrated high-current drivers allow using different types of power
MOSFETs (also multiple MOS to reduce the equivalent RDS(on)), maintaining fast switching
transition.
The driver for the high-side MOSFET use BOOT pin for supply and PHASE pin for return.
The driver for the low-side MOSFET use the VCC pin for supply and PGND pin for return.
The driver embodies a anti-shoot-through and adaptive dead-time control to minimize Low-
Side body diode conduction time maintaining good efficiency saving the use of Schottky
diodes: when the high-side MOSFET turns off, the voltage on its source begins to fall; when
the voltage reaches about 2 V, the low-side MOSFET gate drive voltage is suddenly applied.
When the low-side MOSFET turns off, the voltage at LGATE pin is sensed. When it drops
below about 1 V, the high-side MOSFET gate drive voltage is suddenly applied. If the
current flowing in the inductor is negative, the source of highside MOSFET will never drop.
To allow the low-side MOSFET to turn-on even in this case, a watchdog controller is
enabled: if the source of the high-side MOSFET doesn't drop, the low-side MOSFET is
switched on so allowing the negative current of the inductor to recirculate. This mechanism
allows the system to regulate even if the current is negative.
Before VCC to overcome the UVLO threshold, L6743, L6743Q keeps firmly-OFF both high-
side and low-side MOSFETS then, after the UVLO has been crossed, the EN and PWM
inputs take the control over driver’s operations. EN pin enables the driver: if low will keep all
MOSFET OFF (HiZ) regardless of the status of PWM. When EN is high, the PWM input
takes the control: if left floating, the internal resistor divider sets the HiZ state: both
MOSFETS are kept in the OFF state until PWM transition.
After UVLO crossing and while in HiZ, the preliminary-OV protection is activated: if the
voltage senses through the PHASE pin overcomes about 1.8 V, the low-side MOSFET is
latched ON in order to protect the load from dangerous over-voltage. The driver status is
reset from a PWM transition.
Driver power supply as well as power conversion input are flexible: 5 V and 12 V can be
chosen for high-side and low-side MOSFET voltage drive.
Figure 4. Timing diagram (EN = High)
Device description and operation L6743, L6743Q
8/17
5.1 High-impedance (HiZ) management
The driver is able to manage high-impedance state by keeping all MOSFETs in off state in
two different ways. If the EN signal is pulled low, the device will keep all MOSFETs OFF careless of the
PWM status. When EN is asserted, if the PWM signal remains in the HiZ window for a time longer
than the hold-off time, the device detects the HiZ condition so turning off all the
MOSFETs. The HiZ window is defined as the PWM voltage range comprised between
VPWM_IL and VPWM_IH.
The device exits from the HiZ state only after a PWM transition to logic zero (VPWM <
VPWM_IL).
See Figure 4 for details about HiZ timings.
The implementation of the high-impedance state allows the controller that will be connected
to the driver to manage high-impedance state of its output, avoiding to produce negative
undershoot on the regulated voltage during the shut-down stage. Furthermore, different
power management states may be managed such as pre-bias start-up.
5.2 Preliminary OV protection
After VCC has overcome its UVLO threshold and while in HiZ, L6743, L6743Q activates the
Preliminary-OV protection.
The intent of this protection is to protect the load especially from high-side MOSFET failures
during the system start-up. In fact, VRM, and more in general PWM controllers, have a 12 V
bus compatible turn-on threshold and results to be non-operative if VCC is below that turn-
on thresholds (that results being in the range of about 10 V). In case of a high-side MOSFET
failure, the controller won’t recognize the over voltage until VCC = ~10 V (unless other
special features are implemented): but in that case the output voltage is already at the same
voltage (~10 V) and the load (CPU in most cases) already burnt.
L6743, L6743Q by-pass the PWM controller by latching on the low-side MOSFET in case
the PHASE pin voltage overcome 2 V during the HiZ state. When the PWM input exits form
the HiZ window, the protection is reset and the control of the output voltage is transferred to
the controller connected to the PWM input.
Since the driver has its own UVLO threshold, a simple way to provide protection to the
output in all conditions when the device is OFF consists in supplying the controller through
the 5 VSB bus: 5 VSB is always present before any other voltage and, in case of High-Side
short, the low-side MOSFET is driven with 5 V assuring a reliable protection of the load.
Preliminary OV is active after UVLO and while the driver is in HiZ state and it is disabled
after the first PWM transition. The controller will have to manage its output voltage from that
time on.
L6743, L6743Q Device description and operation
9/17
5.3 Internal BOOT diode
L6743, L6743Q embeds a boot diode to supply the high-side driver saving the use of an
external component. Simply connecting an external capacitor between BOOT and PHASE
complete the high-side supply connections.
To prevent bootstrap capacitor to extra-charge as a consequence of large negative spikes,
an external series resistance RBOOT (in the range of few ohms) may be required in series to
BOOT pin.
Bootstrap capacitor needs to be designed in order to show a negligible discharge due to the
high-side MOSFET turn-on. In fact it must give a stable voltage supply to the high-side driver
during the MOSFET turn-on also minimizing the power dissipated by the embedded Boot
Diode. Figure 5 gives some guidelines on how to select the capacitance value for the
bootstrap according to the desired discharge and depending on the selected MOSFET.
Figure 5. Bootstrap capacitance design
5.4 Power dissipation
L6743, L6743Q embeds high current drivers for both high-side and low-side MOSFETs: it is
then important to consider the power that the device is going to dissipate in driving them in
order to avoid overcoming the maximum junction operative temperature.
Two main terms contribute in the device power dissipation: bias power and drivers' power. Device power (PDC) depends on the static consumption of the device through the
supply pins and it is simply quantifiable as follow: Drivers' power is the power needed by the driver to continuously switch ON and OFF
the external MOSFETs; it is a function of the switching frequency and total gate charge
of the selected MOSFETs. It can be quantified considering that the total power PSW
dissipated to switch the MOSFETs dissipated by three main factors: external gate
resistance (when present), intrinsic MOSFET resistance and intrinsic driver resistance.
This last term is the important one to be determined to calculate the device power
dissipation.
The total power dissipated to switch the MOSFETs results:DC VCCICC V PVCCI PVCC⋅+⋅=SW FSW Q GHS PVCC⋅ Q GLS VCC⋅+ ()⋅=
