L6731D ,Adjustable step-down controller with synchronous rectification dedicated to DDR memoryElectrical characteristics . . . . . 85 Device description . 105.1 Oscillator . 1 ..
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L6731D-L6731DTR
Adjustable step-down controller with synchronous rectification dedicated to DDR memory
June 2008 Rev 3 1/23
L6731DAdjustable step-down controller with synchronous rectification
dedicated to DDR memory
Features Input voltage range from 1.8 V to 14 V Supply voltage range from 4.5 V to 14 V Adjustable output voltage down to 0.6 V with
±0.8 % Accuracy over line voltage and
temperature (0 °C~125 °C) Fixed frequency voltage mode control TON lower than 100 ns 0 % to 100 % duty cycle VDDR input sense Regulates VTT and VTTREF within 1 % of VDDQ Soft-start and inhibit High current embedded drivers Predictive anti-cross conduction control Programmable high-side and low-side RDS(on)
sense over-current-protection Selectable switching frequency 250 kHz /
500 kHz Power good output Sink/source capability for DDR memory and
termination supply Over-voltage protection Thermal shutdown Package: HTSSOP16
Applications High performance / high density DC-DC
modules Low voltage distributed DC-DC niPoL converters DDR memory supply DDR termination supply Graphic cards
Table 1. Device summary
Contents L6731D2/23
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 11
5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.8 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.9 HICCUP mode during an OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.10 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.11 Minimum on-time (TON, MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
L6731D Summary description
3/23
1 Summary description
The controller is an integrated circuit realized in BCD5 (BiCMOS-DMOS, version 5)
fabrication that provides complete control logic and protection for high performance
step-down DC-DC and niPoL converters.
It is designed to drive N-channel MOSFETs in a synchronous rectified buck topology. The
output voltage of the converter can be precisely regulated down to 600 mV with a maximum
tolerance of ±0.8 %. If an external reference is used, it will be transferred divided by 2 to the
N.I. input of the error-amplifier, in accordance to the DDR memory specifications.
An internal resistor divider and a voltage buffer allow to achieve an accuracy of 1 % on both
Vtt and Vttref. It's possible to provide an external reference from 0V to 2.5 V in order to meet
the specification for DDRI and DDRII. The input voltage can range from 1.8 V to 14 V , while
the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for
fast switching to the external power section, and the output current can be in excess of 20 A.
The PWM duty cycle can range from 0 % to 100 % with a minimum on-time (TON, MIN) lower
than 100 ns making possible conversions with very low duty cycle at high switching
frequency. The device provides voltage-mode control that includes a selectable frequency
oscillator (250 kHz or 500 kHz).
The error amplifier features a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that
permits to realize high converter bandwidth for fast transient response. The device monitors
the current by using the RDS(on) of both the high-side and low-side MOSFET(s), eliminating
the need for a current sensing resistor and guaranteeing an effective over-current-protection
in all the application conditions.
When necessary, two different current limit protections can be externally set through two
external resistors. During the soft-start phase a constant current protection is provided while
after the soft-start the device enters in hiccup mode in case of over-current. The converter
can always sink current. Other features are power good, not latched over-voltage-protection,
feed-back disconnection and thermal shutdown. The HTSSOP16 package allows the
realization of really compact DC/DC converters.
Summary description L6731D
4/23
1.1 Functional description
Figure 1. Block diagram
L6731D Electrical data
5/23
2 Electrical data
2.1 Maximum rating
2.2 Thermal data
Table 2. Absolute maximum ratings
Table 3. Thermal data Package mounted on demonstration board
Pin connections and functions L6731D
6/23
Pin connections and functions
L6731D Pin connections and functions
7/23
Table 4. Pin functions (continued)
Electrical characteristics L6731D
8/23
4 Electrical characteristics
VCC = 12 V, TA = 25 °C unless otherwise specified.
Table 5. Electrical characteristics
L6731D Electrical characteristics
9/23
Table 5. Electrical characteristics (continued)
Table 6. Thermal characteristics (VCC = 12 V)
Device description L6731D
10/23
5 Device description
5.1 Oscillator
The switching frequency can be fixed to two values: 250 kHz or 500 kHz by setting the
proper voltage at the EAREF pin (see Table 4. Pins function and section 4.3 Internal and
external reference).
5.2 Internal LDO
An internal LDO supplies the internal circuitry of the device. The input of this stage is the
VCC pin and the output (5 V) is the VCCDR pin (Figure 3.).
The LDO can be by-passed, providing directly a 5 V voltage to V CCDR . In this case VCC and CCDR pins must be shorted together as shown in Figure 4. V CCDR pin must be filtered with
at least 1 µF capacitor to sustain the internal LDO during the recharge of the bootstrap
capacitor. V CCDR also represents a voltage reference for PGOOD pin (see Table 4. Pins
Function).
Figure 3. LDO block diagram
L6731D Device description
11/23
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc
If VCC ≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω. The
maximum LDO output current is about 100 mA and so the output voltage drop is 100 mV, to
avoid this the LDO can be bypassed.
5.4 Internal and external references
It is possible to set the internal/external reference and the switching frequency by setting the
proper voltage at the DDR-IN pin. The maximum value of the external reference is 2.5 V
(typ.): V EAREF from 0 % to 80 % of V CCDR -> External reference/FSW = 250 kHz VEAREF from 80 % to 95 % of VCCDR -> VREF = 0.6 V/FSW = 500 kHz VEAREF from 95 % to 100 % of VCCDR -> VREF = 0.6 V/FSW = 250 kHz
Providing an external reference from 0V to 450mV the output voltage will be regulated but
some restrictions must be considered: OV threshold saturates to a minimum value of 300 mV (OV is tracking the
reference; tracking small references will result in a narrow threshold reducing
noise immunity) The under-voltage-protection doesn't work; The PGOOD signal remains low;
To set the resistor divider it must be considered that a 100 k pull-down resistor is integrated
into the device (see Figure 5.). Finally it must be taken into account that the voltage at the
DDR-IN pin is captured by the device at the start-up when VCC is about 4 V.
Figure 4. Bypassing the LDO
Device description L6731D
12/23
5.5 Error amplifier
5.6 Soft-start
When both VCC and VIN are above their turn-ON thresholds (VIN is monitored by the OCH
pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At
start-up, a ramp is generated charging the external capacitor CSS with an internal current
generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5V.
After that it becomes 10 µA until the final charge value of approximately 4 V (see Figure 6.).
Figure 5. Error amplifier reference
Figure 6. Device start-up: voltage at the SS pin
