L6730B ,Adjustable step-down controller with synchronous rectificationfeatures include Master-Slave synchronization (with 180° phase shift), Power-Good with adjustable d ..
L6730BTR ,Adjustable step-down controller with synchronous rectificationfeatures a 10 MHz gain-bandwidth-product and 5 V/µs slew-rate that permits to realize high converte ..
L6730C ,Adjustable step-down controller with synchronous rectificationElectrical characteristics . . . . . . 105 Device description . . . . 135.1 Oscillator ..
L6730TR ,Adjustable step-down controller with synchronous rectificationFeatures■ Input voltage range from 1.8 V to 14 V ■ Supply voltage range from 4.5 V to 14 V■ Adjusta ..
L6731D ,Adjustable step-down controller with synchronous rectification dedicated to DDR memoryElectrical characteristics . . . . . 85 Device description . 105.1 Oscillator . 1 ..
L6731DTR ,Adjustable step-down controller with synchronous rectification dedicated to DDR memoryApplications■ High current embedded drivers ■ Predictive anti-cross conduction control ■ High perfo ..
LC4064V-75T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75T48I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75TN100I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4064V-75TN44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6730-L6730B-L6730BTR-L6730TR
Adjustable step-down controller with synchronous rectification
December 2009 Doc ID 11938 Rev 3 1/52
L6730
L6730BAdjustable step-down controller with synchronous rectification
Features Input voltage range from 1.8 V to 14 V Supply voltage range from 4.5 V to 14 V Adjustable output voltage down to 0.6 V with
±0.8% accuracy over line voltage and
temperature (0°C~125°C) Fixed frequency voltage mode control tON lower than 100 ns 0% to 100% duty cycle Selectable 0.6 V or 1.2 V internal voltage
reference External input voltage reference Soft-start and inhibit High current embedded drivers Predictive anti-cross conduction control Selectable uvlo threshold (5 V or 12 V BUS) Programmable high-side and low-side RDS(on)
sense overcurrent protection Switching frequency programmable
from 100 kHz to 1 MHz Master/slave synchronization with 180° phase
shift Pre-bias start up capability (L6730) Selectable source/sink or source only
capability after soft-start (L6730) Selectable constant current or hiccup mode
overcurrent protection after soft-start (L6730B) Power Good output with programmable delay Overvoltage protection with selectable
latched/not-latched mode Thermal shut-down Package: HTSSOP20
Applications High performance / high density DC-DC
modules Low voltage distributed DC-DC niPOL converters DDR memory supply DDR memory bus termination supply
Table 1. Device summary
Contents L6730 - L6730B2/52 Doc ID 11938 Rev 3
Contents Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 15
5.4 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8 Monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.9 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.10 Multifunction pin (S/O/U L6730) (CC/O/U L6730B) . . . . . . . . . . . . . . . . . 27
5.11 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.12 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.13 Minimum ON-time TON(MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.14 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.14.1 Fan power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.14.2 No-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
L6730 - L6730B ContentsDoc ID 11938 Rev 3 3/52
6.2 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5 T wo quadrant or one quadrant operation mode (L6730) . . . . . . . . . . . . . 37
L6730 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 POL demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Summary description L6730 - L6730B
4/52 Doc ID 11938 Rev 3
1 Summary description
The controller is an integrated circuit designed using BiCMOS-DMOS, v5 (BCD5)
technology that provides complete control logic and protection for high performance, step-
down DC/DC and niPOL converters.
It is designed to drive N-Channel MOSFETs in a synchronous rectified buck converter
topology. The output voltage of the converter can be precisely regulated down to 600 mV,
with a maximum tolerance of ±0.8%, or to 1.2 V, when one of the internal references is used.
It is also possible to use an external reference from 0 V to 2.5 V.
The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5
V to 14 V . High peak current gate drivers provide for fast switching to the external power
section and the output current can be in excess of 20 A, depending on the number of the
external MOSFETs used. The PWM duty cycle can range from 0% to 100% with a minimum
on-time (TON(MIN)) lower than 100 ns, making conversions with a very low duty cycle and
very high switching frequency possible.
The device provides voltage-mode control. It includes a 400 kHz free-running oscillator that
is adjustable from 100 kHz to 1 MHz. The error amplifier features a 10 MHz gain-bandwidth-
product and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast
transient response. The device monitors the current by using the RDS(ON) of both the high-
side and low-side MOSFET(s), eliminating the need for a current sensing resistor and
guaranteeing an effective over current-protection in all the application conditions. When
necessary, two different current limit protections can be externally set through two external
resistors. A leading edge adjustable blanking time is also available to avoid false over-
current-protection (OCP) intervention in every application condition.
It is possible to select the HICCUP mode or the constant current protection (L6730B) after
the soft-start phase.
During this phase constant current protection is provided. It is possible to select the sink-
source or the source-only mode capability (before the device powers on) by acting on a
multifunction pin (L6730). The L6730 disables the sink mode capability during the soft-start
in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730B
can always sink current and, so it can be used to supply the DDR memory BUS termination.
Other features include Master-Slave synchronization (with 180° phase shift), Power-Good
with adjustable delay, over voltage-protection, feed back disconnection, selectable UVLO
threshold (5 V and 12 V Bus), and thermal shutdown. The HTSSOP20 package allows the
realization for very compact DC/DC converters.
L6730 - L6730B Summary description
Doc ID 11938 Rev 3 5/52
1.1 Functional description
Note: In the L6730B the multifunction pin is: CC/OVP/UVLO.
Figure 1. Block diagram
