L6566BTR ,Multi-mode controller for SMPSElectrical characteristics . . . . 125 Application information . . . . . 175.1 High-volta ..
L6567 ,HIGH VOLTAGE DRIVER FOR CFLBLOCK DIAGRAMVhvRhv Cp/CavRHV CP13 8V 5 1 F VhvS SVSHIGH 2 G1PREHEATING LEVEL FEED FORWARD T1SIDE T ..
L6567D ,HIGH VOLTAGE DRIVER FOR CFLBLOCK DIAGRAMVhvRhv Cp/CavRHV CP13 8V 5 1 F VhvS SVSHIGH 2 G1PREHEATING LEVEL FEED FORWARD T1SIDE T ..
L6567D ,HIGH VOLTAGE DRIVER FOR CFLL6567HIGH VOLTAGE DRIVER FOR CFLn BCD-OFF LINE TECHNOLOGYMULTIPOWER BCD TECHNOLOGYn FLOATING SUPPLY ..
L6569 ,HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitI (*) Supply Current 25 mASV Oscillator Resistor ..
L6569A ,HIGH VOLTAGE HALF BRIDGE DRIVER WITH OSCILLATORABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitI (*) Supply Current 25 mASV Oscillator Resistor ..
LC4032B-75T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032C-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-10TN44I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-25TN48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-5T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6566B-L6566BTR
Multi-mode controller for SMPS
December 2008 Rev 3 1/51
L6566BMulti-mode controller for SMPS
Features Selectable multi-mode operation:
fixed frequency or quasi-resonant On-board 700 V high-voltage start-up Advanced light load management Low quiescent current (< 3 mA) Adaptive UVLO Line feedforward for constant power capability
vs mains voltage Pulse-by-pulse OCP, shutdown on overload
(latched or autorestart) Transformer saturation detection Programmable frequency modulation for EMI
reduction Latched or autorestart OVP Brownout protection -600/+800 mA totem pole gate driver with
active pull-down during UVLO SO16N package
Applications Hi-end AC-DC adapter/charger LCD TV/monitor, PDP digital consumer, IT equipment single-stage PFC
Figure 1. Block diagram
Contents L6566B2/51
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175.1 High-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Zero current detection and triggering block; oscillator block . . . . . . . . . . 21
5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24
5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 27
5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.8 Frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 33
5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.14 Summary of L6566B power management functions . . . . . . . . . . . . . . . . 41
L6566B Contents 3/51
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables L6566B
4/51
List of tables
Table 2. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 6. L6566B light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7. L6566B protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 45
Table 9. SO16N mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
L6566B List of figures
5/51
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multi-mode operation with QR option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5. High-voltage start-up generator: internal schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5V). . . . . . . . . . . . . . . 20
Figure 8. Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 20
Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 23
Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold. . . . 25
Figure 13. Adaptive UVLO block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Possible feedback configurations that can be used with the L6566B. . . . . . . . . . . . . . . . . 26
Figure 15. Externally controlled burst-mode operation by driving pin COMP: timing diagram. . . . . . . 27
Figure 16. Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 28
Figure 17. Left: Overcurrent setpoint vs. VFF voltage; right: Line Feedforward function block . . . . . . 29
Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Frequency modulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Operation after latched disable activation: timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 34
Figure 22. OVP Function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 37
Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Voltage sensing techniques to implement brownout protection with the L6566B. . . . . . . . 39
Figure 27. Slope compensation waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28. Typical low-cost application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Description L6566B
6/51
1 Description
The L6566B is an extremely versatile current-mode primary controller ICs, specifically
designed for high-performance offline flyback converters. It is also suited for single-stage
single-switch input-current-shaping converters (single-stage PFC) for applications supposed
to comply with EN61000-3-2 or JEITA-MITI regulations.
Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can
pick either of the two depending on application needs. The device features an externally
programmable oscillator: it defines converter’s switching frequency in FF mode and the
maximum allowed switching frequency in QR mode.
When FF operation is selected, the ICs work like a standard current-mode controller with a
maximum duty cycle limited at 70 % min. The oscillator frequency can be modulated to
mitigate EMI emissions.
QR operation, when selected, occurs at heavy load and is achieved through a transformer
demagnetization sensing input that triggers MOSFET’s turn-on. Under some conditions,
ZVS (zero-voltage switching) can be achieved. Converter’s power capability rise with the
mains voltage is compensated by line voltage feedforward. At medium and light load, as the
QR operating frequency equals the oscillator frequency, a function (valley skipping) is
activated to prevent further frequency rise and keep the operation as close to ZVS as
possible.
With either FF or QR operation, at very light load the ICs enter a controlled burst-mode
operation that, along with the built-in non-dissipative high-voltage start-up circuit and the low
quiescent current, helps keep low the consumption from the mains and meet energy saving
recommendations.
An innovative adaptive UVLO helps minimize the issues related to the fluctuations of the
self-supply voltage due to transformer’s parasites.
The protection functions included in this device are: not-latched input undervoltage
(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with
delayed shutdown to protect the system during overload or short circuit conditions (auto-
restart or latch-mode selectable) and a second-level OCP that is invoked when the
transformer saturates or the secondary diode fails short. A latched disable input allows easy
implementation of OTP with an external NTC, while an internal thermal shutdown prevents
IC overheating.
Programmable soft-start, leading-edge blanking on the current sense input for greater noise
immunity, slope compensation (in FF mode only), and a shutdown function for externally
controlled burst-mode operation or remote ON/OFF control complete the equipment of this
device.
L6566B Description
7/51
Figure 2. Typical system block diagram
Pin settings L6566B
8/51
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
2.2 Pin description
Table 1. Pin functions
L6566B Pin settings
9/51
Table 1. Pin functions (continued)
Pin settings L6566B
10/51
Table 1. Pin functions (continued)
L6566B Electrical data
11/51
3 Electrical data
3.1 Maximum rating
3.2 Thermal data
Table 2. Absolute maximum ratings
Table 3. Thermal data
Electrical characteristics L6566B
12/51
4 Electrical characteristics
(TJ = -25 to 125°C, VCC = 12, CO = 1 nF; MODE/SC = VREF, RT = 20 kΩ from OSC to GND,
unless otherwise specified).
Table 4. Electrical characteristics
L6566B Electrical characteristics
13/51
Table 4. Electrical characteristics (continued)
Electrical characteristics L6566B
14/51
Table 4. Electrical characteristics (continued)
L6566B Electrical characteristics
15/51
Table 4. Electrical characteristics (continued)
Electrical characteristics L6566B
16/51 Parameters tracking one another. See Table 6 on page 41 and Table 7 on page42 The voltage feedforward block output is given by:
Table 4. Electrical characteristics (continued)
L6566B Application information
17/51
5 Application information
The L6566B is a versatile peak-current-mode PWM controller specific for offline flyback
converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation,
selectable with the pin MODE/SC (12): forcing the voltage on the pin over 3 V (e.g. by tying
it to the 5 V reference externally available at pin VREF, 10) will activate QR operation,
otherwise the device will be FF-operated.
Irrespective of the operating option selected by pin 12, the device is able to work in different
modes, depending on the converter’s load conditions. If QR operation is selected (see
Figure4): QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET's
turn-on to the transformer’s demagnetization by detecting the resulting negative-going
edge of the voltage across any winding of the transformer. Then the system works
close to the boundary between discontinuous (DCM) and continuous conduction
(CCM) of the transformer. As a result, the switching frequency will be different for
different line/load conditions (see the hyperbolic-like portion of the curves in Figure 4).
Minimum turn-on losses, low EMI emission and safe behavior in short circuit are the
main benefits of this kind of operation.
2. Valley-skipping mode at medium/ light load. The externally programmable oscillator of
the L6566B, synchronized to MOSFET’s turn-on, enables the designer to define the
maximum operating frequency of the converter. As the load is reduced MOSFET’s turn-
on will not any more occur on the first valley but on the second one, the third one and
so on. In this way the switching frequency will no longer increase (piecewise linear
portion in Figure 4).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter will enter a controlled on/off operation with constant peak current.
Decreasing the load will then result in frequency reduction, which can go down even to
few hundred hertz, thus minimizing all frequency-related losses and making it easier to
comply with energy saving regulations or recommendations. Being the peak current
very low, no issue of audible noise arises.
Figure 4. Multi-mode operation with QR option active
Application information L6566B
18/51
If FF operation is selected: FF mode from heavy to light load. The system operates exactly like a standard current
mode control, at a frequency fsw determined by the externally programmable oscillator:
both DCM and CCM transformer operation are possible, depending on whether the
power that it processes is greater or less than:
Equation 1
where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the
regulated output voltage times the primary-to-secondary turn ratio) and Lp the
inductance of the primary winding. PinT is the power level that marks the transition from
continuous to discontinuous operation mode of the transformer.
2. Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation.
The L6566B is specifically designed for applications with no PFC front-end; pin 6 (FMOD)
features an auxiliary oscillator that can modulate the switching frequency (when FF
operation is selected) in order to mitigate EMI emissions by a spread-spectrum action.
5.1 High-voltage start-up generator
Figure 5 shows the internal schematic of the high-voltage start-up generator (HV generator).
It is made up of a high-voltage N-channel FET, whose gate is biased by a 15 MΩ resistor,
with a temperature-compensated current generator connected to its source.
Figure 5. High-voltage start-up generator: internal schematic
L6566B Application information
19/51
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is
enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus
the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to
ground and makes its voltage rise almost linearly.
Figure 6. Timing diagram: normal power-up and power-down sequences
As the Vcc voltage reaches the turn-on threshold (14 V typ.) the device starts operating and
the HV generator is cut off by the Vcc_OK signal asserted high. The device is powered by
the energy stored in the Vcc capacitor until the self-supply circuit (typically an auxiliary
winding of the transformer and a steering diode) develops a voltage high enough to sustain
the operation. The residual consumption of this circuit is just the one on the 15 MΩ resistor
(≈10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as compared
to a standard start-up circuit made with external dropping resistors.
At converter power-down the system will lose regulation as soon as the input voltage is so
low that either peak current or maximum duty cycle limitation is tripped. Vcc will then drop
and stop IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is
de-asserted as the Vcc voltage goes below a threshold VCCrest located at about 5V . The HV
generator can now restart. However, if Vin < Vin start , as illustrated in Figure 6, HV_EN is de-
asserted too and the HV generator is disabled. This prevents converter’s restart attempts
and ensures monotonic output voltage decay at power-down in systems where brownout
protection (see the relevant section) is not used.
The low restart threshold VCCrest ensures that, during short circuits, the restart attempts of
the device will have a very low repetition rate, as shown in the timing diagram of Figure 7 on
page 20, and that the converter will work safely with extremely low power throughput.
Application information L6566B
20/51
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V)
Figure 8. Zero current detection block, triggering block, oscillator block and
related logic
L6566B Application information
21/51
5.2 Zero current detection and triggering block; oscillator block
The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a
negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is typically used to detect transformer demagnetization for QR operation, where
the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the L6566B. The triggering block is blanked for TBLANK = 2.5 µs after MOSFET’s
turn-off to prevent any negative-going edge that follows leakage inductance
demagnetization from triggering the ZCD circuit erroneously.
The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of Figure 8 on page 20. The upper clamp is typically
located at 5.7 V, while the lower clamp is located at -0.4 V. The interface between the pin
and the auxiliary winding will be a resistor divider. Its resistance ratio will be properly chosen
(see Section 5.11: OVP block on page 35) and the individual resistance values (RZ1, RZ2)
will be such that the current sourced and sunk by the pin be within the rated capability of the
internal clamps (± 3 mA).
At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up
the system. The oscillator is programmed externally by means of a resistor (RT) connected
from pin OSC (13) to ground. With good approximation the oscillation frequency fosc will be:
Equation 2
(with fosc in kHz and RT in kΩ). As the device is turned on, the oscillator starts immediately;
at the end of the first oscillator cycle, being zero the voltage on the ZCD pin, the MOSFET
will be turned on, thus starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (hence a negative-going edge appears
on the ZCD pin) after a time exceeding one oscillation period Tosc = 1/fosc from the previous
turn-on, the MOSFET will be turned on again - with some delay to ensure minimum voltage
at turn-on – and the oscillator ramp will be reset. If, instead, the negative-going edge
appears before Tosc has elapsed, it will be ignored and only the first negative-going edge
after Tosc will turn-on the MOSFET and synchronize the oscillator. In this way one or more
drain ringing cycles will be skipped (“valley-skipping mode”, Figure 9) and the switching
frequency will be prevented from exceeding fosc.
Application information L6566B
22/51
Note: When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching
cycles will be compensated by one or more shorter cycles and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET’s turn-on cannot be triggered. This case is identical to what happens at start-up:
at the end of the next oscillator cycle the MOSFET will be turned on, and a new switching
cycle will take place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time T BLANK after MOSFET’s
turn off, and actually T BLANK does not come into play as long as the following condition is
met:
Equation 3
where D is the MOSFET duty cycle. If this condition is not met, things do not change
substantially: the time during which MOSFET’s turn-on is inhibited is extended beyond Tosc
by a fraction of T BLANK . As a consequence, the maximum switching frequency will be a little
lower than the programmed value fosc and valley-skipping mode may take place slightly
earlier than expected. However this is quite unusual: setting fosc = 150 kHz, the
phenomenon can be observed at duty cycles higher than 60 %. See Section 5.11: OVP
block on page 35 for further implications of T BLANK.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET's OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin might not
be able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, however ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET's turn-on is that of the external oscillator
divided by 128. Additionally, to prevent malfunction at converter's start-up, the pull-up is
disabled during the initial soft-start (see the relevant section). However, to ensure a correct
Figure 9. Drain ringing cycle skipping as the load is gradually reduced
L6566B Application information
23/51
start-up, at the end of the soft-start phase the output voltage of the converter must meet the
condition:
Equation 4
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding and IZCD the maximum pull-up current (130 μA).
The operation described so far under different operating conditions for the converter is
illustrated in the timing diagrams of Figure 10.
If the FF option is selected the operation will be exactly equal to that of a standard current-
mode PWM controller. It will work at a frequency fsw = fosc; both DCM and CCM
transformer's operation are possible, depending on the operating conditions (input voltage
and output load) and on the design of the power stage. The MOSFET is turned on at the
beginning of each oscillator cycle and is turned off as the voltage on the current sense pin
reaches an internal reference set by the line feedforward block. The maximum duty cycle is
limited at 70 % minimum. The signal on the ZCD pin in this case is used only for detecting
feedback loop failures (see Section 5.11: OVP block on page 35).
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active)
Application information L6566B
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5.3 Burst-mode operation at no load or very light load
When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a
value, VCOMPBM, depending on the selected operating mode, the L6566B is disabled with
the MOSFET kept in OFF state and its consumption reduced at a lower value to minimize
Vcc capacitor discharge.
The control voltage now will increase as a result of the feedback reaction to the energy
delivery stop (the output voltage will be slowly decaying), the threshold will be exceeded and
the device will restart switching again. In this way the converter will work in burst-mode with
a nearly constant peak current defined by the internal disable level. A load decrease will
then cause a frequency reduction, which can go down even to few hundred hertz, thus
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. This kind of operation, shown in the timing diagrams of Figure 11 along with the
others previously described, is noise-free since the peak current is low.
If it is necessary to decrease the intervention threshold of the burst-mode operation, this can
be done by adding a small DC offset on the current sense pin as shown in Figure 12 on
page 25.
Note: The offset reduces the available dynamics of the current signal; thereby, the value of the
sense resistor must be determined taking this offset into account.
Figure 11. Load-dependent operating modes: timing diagrams
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Figure 12. Addition of an offset to the current sense lowers the burst-mode
operation threshold
5.4 Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to a few mA load. This very often causes the supply voltage Vcc of the
control IC to drop and go below the UVLO threshold so that the operation becomes
intermittent, which is undesired. Furthermore, this must be traded off against the need of
generating a voltage not exceeding the maximum allowed by the control IC at full load. o help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at pin COMP falls below a threshold V COMPO internally fixed, so as to have more
headroom. To prevent any malfunction during transients from minimum to maximum load
the normal (higher) UVLO threshold is re-established when the voltage at pin COMP
exceeds V COMPL and Vcc has exceeded the normal UVLO threshold (see Figure 13). The
normal UVLO threshold ensures that at full load the MOSFET will be driven with a proper
gate-to-source voltage.
Figure 13. Adaptive UVLO block
Application information L6566B
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5.5 PWM control block
The device is specific for secondary feedback. Typically, there is a TL431 on the secondary
side and an optocoupler that transfers output voltage information to the PWM control on the
primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the
duty cycle (Figure 14, left-hand side circuit).
In applications where a tight output regulation is not required, it is possible to use a primary-
sensing feedback technique. In this approach the voltage generated by the self-supply
winding is sensed and regulated. This solution, shown in Figure 14, right-hand side circuit,
is cheaper because no optocoupler or secondary reference is needed, but output voltage
regulation, especially as a result of load changes, is quite poor.
Figure 14. Possible feedback configurations that can be used with the L6566B
Ideally, the voltage generated by the self-supply winding and the output voltage should be
related by the Naux/Ns turn ratio only. Actually, numerous non-idealities, mainly
transformer's parasites, cause the actual ratio to deviate from the ideal one. Line regulation
is quite good, in the range of ± 2 %, whereas load regulation is about ± 5 % and output
voltage tolerance is in the range of ± 10 %.
The dynamics of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped
downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is
pulled below 1.4 V the L6566B will shut down. This condition is latched as long as the
device is supplied. While the device is disabled, however, no energy is coming from the self-
supply circuit, thus the voltage on the Vcc capacitor will decay and cross the UVLO
threshold after some time, which clears the latch and lets the HV generator restart. This
function is intended for an externally controlled burst-mode operation at light load with a
reduced output voltage, a technique typically used in multi-output SMPS, such as those for
TVs or monitors (see the timing diagram Figure 15 on page 27).
