L6566ATR ,Multi-mode controller for SMPS with PFC front-endElectrical characteristics . . . . 115 Application information . . . . . 155.1 High-volta ..
L6566B ,Multi-mode controller for SMPSBlock diagramVREF SS COMP VFF10 14 9 CCV15 6.4VLOW CLAMPTIMEOVPLOVP1 &DISABLESOFT-START OUT1mAHV &O ..
L6566B ,Multi-mode controller for SMPSblock diagram 7Figure 3. Pin connection (through top view) . . . . 8Figure 4. Multi-mode ..
L6566BH ,Multi-mode controller for SMPSElectrical characteristics . . . . 125 Application information . . . . . 165.1 High volta ..
L6566BHTR ,Multi-mode controller for SMPSblock diagram 7Figure 3. Pin connection (through top view) . . . . 8Figure 4. Multimode o ..
L6566BTR ,Multi-mode controller for SMPSElectrical characteristics . . . . 125 Application information . . . . . 175.1 High-volta ..
LC4032B-75T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032C-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-10TN44I , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-25TN48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-5T44C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4032V-75T48C , 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
L6566A-L6566ATR
Multi-mode controller for SMPS with PFC front-end
Doc ID 13794 Rev 4 1/52
L6566AMulti-mode controller for SMPS with PFC front-end
Datasheet − production data
Features Selectable multi-mode operation: fixed
frequency or quasi-resonant Onboard 700 V high-voltage startup Advanced light load management Low quiescent current (< 3 mA) Adaptive UVLO Line feedforward for constant power capability
vs. mains voltage Pulse-by-pulse OCP, shutdown on overload
(latched or auto-restart) Transformer saturation detection Switched supply rail for PFC controller Latched or auto-restart OVP Brownout protection -600/+800 mA totem pole gate-driver with
active pull-down during UVLO SO16N package
Applications Notebook, TV and LCD monitor adapters High power chargers PDP/LCD TVs Consumer appliances, such as DVD players,
VCRs, set-top boxes IT equipment, games, auxiliary power supplies Power supplies in excess of 150 W
Figure 1. Block diagram
Contents L6566A2/52 Doc ID 13794 Rev 4
Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155.1 High-voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Zero current detection and triggering block; oscillator block . . . . . . . . . . 19
5.3 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22
5.4 Adaptive UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.5 PWM control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.6 PWM comparator, PWM latch and voltage feedforward blocks . . . . . . . . 25
5.7 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 PFC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9 Latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10 Soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 31
5.11 OVP block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.12 Brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.13 Slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.14 Summary of L6566A power management functions . . . . . . . . . . . . . . . . 38
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
L6566A Contents
Doc ID 13794 Rev 4 3/52
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables L6566A
4/52 Doc ID 13794 Rev 4
List of tables
Table 1. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. L6566A light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 6. L6566A protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. External circuits that determine IC behavior upon OVP and OCP . . . . . . . . . . . . . . . . . . . 44
Table 8. SO16N dimentions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 9. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
L6566A List of figures
Doc ID 13794 Rev 4 5/52
List of figures
Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Multi-mode operation with QR option active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5. High-voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6. Timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V) . . . . . . . . . . . . . . 19
Figure 8. Zero current detection block, triggering block, oscillator block and related logic . . . . . . . . 19
Figure 9. Drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active) . . . . . . . . . . . . . . . . 22
Figure 11. Load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Addition of an offset to the current sense lowers the burst-mode operation threshold. . . . 24
Figure 13. Adaptive UVLO block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Possible feedback configurations that can be used with the L6566A. . . . . . . . . . . . . . . . . 25
Figure 15. Externally controlled burst-mode operation by driving the COMP pin: timing diagram. . . . 26
Figure 16. Typical power capability change vs. input voltage in QR flyback converters . . . . . . . . . . . 27
Figure 17. Left: overcurrent setpoint vs. VFF voltage; right: line feedforward function block. . . . . . . . 28
Figure 18. Hiccup-mode OCP: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. Possible interfaces between the L6566A and a PFC controller . . . . . . . . . . . . . . . . . . . . . 31
Figure 20. Operation after latched disable activation: timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. Soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33
Figure 22. OVP function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 23. OVP function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 24. Maximum allowed duty cycle vs. switching frequency for correct OVP detection. . . . . . . . 36
Figure 25. Brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37
Figure 26. AC voltage sensing with the L6566A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 27. Slope compensation waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 28. Typical low-cost application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. Typical full-feature application schematic (QR operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 30. Typical full-feature application schematic (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31. Frequency foldback at light load (FF operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 32. Latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. Package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 34. Recommended footprint (dimensions are in mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Description L6566A
6/52 Doc ID 13794 Rev 4
1 Description
The L6566A is an extremely versatile current-mode primary controller IC specifically
designed for high-performance offline flyback converters operated from front-end power
factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-
MITI regulations.
Both fixed-frequency (FF) and quasi-resonant (QR) operation are supported. The user can
choose either of the two depending on application needs.
The device features an externally programmable oscillator; it defines the converter's
switching frequency in FF mode and the maximum allowed switching frequency in QR
mode.
When FF operation is selected, the IC works like a standard current-mode controller with a
maximum duty cycle limited to 70% (min.).
QR operation, when selected, occurs and is achieved through a transformer
demagnetization sensing input that triggers MOSFET turn-on. Under some conditions, ZVS
(zero-voltage switching) can be achieved. The converter's power capability rise with the
input voltage is compensated by line voltage feedforward. At medium and light load, as the
QR operating frequency equals the oscillator frequency, a function (valley skipping) is
activated to prevent further frequency rise and keep the operation as close to ZVS as
possible.
With either FF or QR operation, at very light load the IC enters a controlled burst-mode
operation that, along with the built-in non-dissipative high-voltage startup circuit and a
reduced quiescent current, helps keep the consumption from the mains low and meet
energy saving recommendations.
To allow the meeting of energy saving recommendations in two-stage power-factor-
corrected systems as well, the L6566A provides an interface with the PFC controller that
enables the re-regulator to be turned off at light load.
An innovative adaptive UVLO helps minimize the issues related to fluctuations in the self-
supply voltage due to transformer parasites.
The protection functions included in this device are: not-latched input undervoltage
(brownout), output OVP (auto-restart or latch-mode selectable), a first-level OCP with
delayed shutdown to protect the system during overload or short-circuit conditions (auto-
restart or latch-mode selectable), and a second-level OCP which is invoked when the
transformer saturates or the secondary diode fails short. A latched disable input allows easy
implementation of OTP with an external NTC, while an internal thermal shutdown prevents
IC overheating.
Programmable soft-start, leading-edge blanking on the current sense input for greater noise
immunity, slope compensation (in FF mode only), and a shutdown function for externally
controlled burst-mode operation or remote ON/OFF control are all features of this device.
L6566A Description
Doc ID 13794 Rev 4 7/52
Pin settings L6566A
8/52 Doc ID 13794 Rev 4
2 Pin settings
2.1 Connections
Figure 3. Pin connection (through top view)
2.2 Pin description
Table 1. Pin functions
L6566A Pin settings
Doc ID 13794 Rev 4 9/52
Table 1. Pin functions (continued)
Pin settings L6566A
10/52 Doc ID 13794 Rev 4
Table 1. Pin functions (continued)
L6566A Electrical data
Doc ID 13794 Rev 4 11/52
3 Electrical data
3.1 Maximum rating
3.2 Thermal data
Table 2. Absolute maximum ratings
Table 3. Thermal data
Electrical characteristics L6566A
12/52 Doc ID 13794 Rev 4
4 Electrical characteristics
(TJ = -25 to 125 °C, VCC = 12 V , CO = 1 nF; MODE/SC = VREF , RT = 20 kΩ from OSC to
GND, unless otherwise specified.)
Table 4. Electrical characteristics
L6566A Electrical characteristics
Doc ID 13794 Rev 4 13/52
Table 4. Electrical characteristics (continued)
Electrical characteristics L6566A
14/52 Doc ID 13794 Rev 4
Table 4. Electrical characteristics (continued)
L6566A Electrical characteristics
Doc ID 13794 Rev 4 15/52 Parameters tracking one another. See Table 6 on page 41 and Table 7 on page45. The voltage feedforward block output is given by:
Table 4. Electrical characteristics (continued)
Application information L6566A
16/52 Doc ID 13794 Rev 4
5 Application information
The L6566A is a versatile peak-current-mode PWM controller specific to offline flyback
converters. The device allows either fixed-frequency (FF) or quasi-resonant (QR) operation,
selectable with the MODE/SC pin (12): forcing the voltage on the pin over 3 V (e.g. by tying
it to the 5 V reference externally available at the VREF pin, 10) activates QR operation,
otherwise the device is FF-operated.
Irrespective of the operating option selected by pin 12, the device is able to work in different
modes, depending on the converter's load conditions. If QR operation is selected (see
Figure4): QR mode at heavy load. Quasi-resonant operation lies in synchronizing MOSFET turn-
on to the transformer's demagnetization by detecting the resulting negative-going edge
of the voltage across any winding of the transformer. The system then works close to
the boundary between discontinuous (DCM) and continuous conduction (CCM) of the
transformer. As a result, the switching frequency is different for different line/load
conditions (see the hyperbolic-like portion of the curves in Figure 4). Minimum turn-on
losses, low EMI emission, and safe behavior in short-circuit are the main benefits of
this kind of operation.
2. Valley-skipping mode at medium/light load. The externally programmable oscillator of
the L6566A, synchronized to MOSFET turn-on, enables the designer to define the
maximum operating frequency of the converter. As the load is reduced, MOSFET turn-
on no longer occurs on the first valley but on the second one, the third one, and so on.
In this way the switching frequency no longer increases (piecewise linear portion in
Figure 4).
3. Burst-mode with no or very light load. When the load is extremely light or disconnected,
the converter enters a controlled on/off operation with constant peak current.
Decreasing the load then results in frequency reduction, which can go down even to a
few hundred hertz, therefore minimizing all frequency-related losses and making it
easier to comply with energy saving regulations or recommendations. Having the peak
current very low, no issue of audible noise arises.
Figure 4. Multi-mode operation with QR option active
L6566A Application information
Doc ID 13794 Rev 4 17/52
If FF operation is selected: FF mode from heavy to light load. The system operates exactly like a standard current
mode, at a frequency fsw determined by the externally programmable oscillator: both
DCM and CCM transformer operations are possible, depending on whether the power
that it processes is greater or less than:
Equation 1
where Vin is the input voltage to the converter, VR the reflected voltage (i.e. the
regulated output voltage times the primary-to-secondary turn ratio) and Lp the
inductance of the primary winding. PinT is the power level that marks the transition from
continuous to discontinuous operation mode of the transformer.
2. Burst-mode with no or very light load. This kind of operation is activated in the same
way and results in the same behavior as previously described for QR operation.
The L6566A is specifically designed for flyback converters operated from front-end power
factor correction (PFC) stages in applications in compliance with EN61000-3-2 or JEITA-
MITI regulations. Pin 6 (Vcc_PFC) provides the supply voltage to the PFC control IC.
5.1 High-voltage startup generator
Figure 5 shows the internal schematic of the high-voltage startup generator (HV generator).
It is made up of a high-voltage N-channel FET, with a gate biased by a 15 MΩ resistor, with
a temperature-compensated current generator connected to its source.
Figure 5. High-voltage startup generator: internal schematic
Application information L6566A
18/52 Doc ID 13794 Rev 4
With reference to the timing diagram of Figure 6, when power is first applied to the converter
the voltage on the bulk capacitor (Vin) builds up and, at about 80 V, the HV generator is
enabled to operate (HV_EN is pulled high) so that it draws about 1 mA. This current, minus
the device’s consumption, charges the bypass capacitor connected from pin Vcc (5) to
ground and causes its voltage to rise almost linearly.
Figure 6. Timing diagram: normal power-up and power-down sequences
As the Vcc voltage reaches the startup threshold (14 V typ.) the low-voltage chip starts
operating and the HV generator is cut off by the Vcc_OK signal asserted high. The device is
powered by the energy stored in the Vcc capacitor until the self-supply circuit (typically an
auxiliary winding of the transformer and a steering diode) develops a voltage high enough to
sustain the operation. The residual consumption of this circuit is just the one on the 15 MΩ
resistor (≈ 10 mW at 400 Vdc), typically 50-70 times lower, under the same conditions, as
compared to a standard startup circuit made with external dropping resistors.
At converter power-down the system loses regulation as soon as the input voltage is so low
that either peak current or maximum duty cycle limitation is tripped. Vcc then drops and
stops IC activity as it falls below the UVLO threshold (10 V typ.). The Vcc_OK signal is de-
asserted as the Vcc voltage goes below a threshold Vcc restart located at about 5 V . The HV
generator can now restart. However, if Vin < Vin start , as illustrated in Figure 6, HV_EN is de-
asserted too and the HV generator is disabled. This prevents converter restart attempts and
ensures monotonic output voltage decay at power-down in systems where brownout
protection (see Section 5.12) is not used.
The low restart threshold Vcc restart ensures that, during short-circuits, the restart attempts of
the device have a very low repetition rate, as shown in the timing diagram of Figure 7 on
page 19, and that the converter works safely with extremely low power throughput.
L6566A Application information
Doc ID 13794 Rev 4 19/52
Figure 7. Timing diagram showing short-circuit behavior (SS pin clamped at 5 V)
Figure 8. Zero current detection block, triggering block, oscillator block and
related logic
Application information L6566A
20/52 Doc ID 13794 Rev 4
5.2 Zero current detection and triggering block; oscillator block
The zero current detection (ZCD) and triggering blocks switch on the external MOSFET if a
negative-going edge falling below 50 mV is applied to the input (pin 11, ZCD). To do so the
triggering block must be previously armed by a positive-going edge exceeding 100 mV.
This feature is typically used to detect transformer demagnetization for QR operation, where
the signal for the ZCD input is obtained from the transformer’s auxiliary winding used also to
supply the L6566A. The triggering block is blanked for TBLANK = 2.5 µs after MOSFET turn-
off to prevent any negative-going edge that follows leakage inductance demagnetization
from triggering the ZCD circuit erroneously.
The voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the
internal diagram of the ZCD block of Figure 8. The upper clamp is typically located at 5.7 V,
while the lower clamp is located at -0.4 V. The interface between the pin and the auxiliary
winding is a resistor divider. Its resistance ratio is properly chosen (see Section 5.11) and
the individual resistance values (RZ1, RZ2) are such that the current sourced and sunk by
the pin be within the rated capability of the internal clamps (± 3 mA).
At converter power-up, when no signal is coming from the ZCD pin, the oscillator starts up
the system. The oscillator is programmed externally by means of a resistor (RT) connected
from pin OSC (13) to ground. With good approximation the oscillation frequency fosc is:
Equation 2
(with fosc in kHz and RT in kW). As the device is turned on, the oscillator starts immediately;
at the end of the first oscillator cycle, the voltage on the ZCD pin being zero, the MOSFET is
turned on, therefore starting the first switching cycle right at the beginning of the second
oscillator cycle. At any switching cycle, the MOSFET is turned off as the voltage on the
current sense pin (CS, 7) hits an internal reference set by the line feedforward block, and the
transformer starts demagnetization. If this completes (so a negative-going edge appears on
the ZCD pin) after a time exceeding one oscillation period Tosc=1/fosc from the previous turn-
on, the MOSFET is turned on again - with some delay to ensure minimum voltage at turn-on
– and the oscillator ramp is reset. If, instead, the negative-going edge appears before Tosc
has elapsed, it is ignored and only the first negative-going edge after Tosc turns on the
MOSFET and synchronizes the oscillator. In this way one or more drain ringing cycles are
skipped (“valley-skipping mode”, Figure 9) and the switching frequency is prevented from
exceeding fosc.
Figure 9. Drain ringing cycle skipping as the load is gradually reduced
L6566A Application information
Doc ID 13794 Rev 4 21/52
Note: When the system operates in valley skipping-mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the OFF-time of the MOSFET
is allowed to change with discrete steps of one ringing cycle, while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Therefore one or more longer switching
cycles is compensated by one or more shorter cycles, and vice versa. However, this
mechanism is absolutely normal and there is no appreciable effect on the performance of
the converter or on its output voltage.
If the MOSFET is enabled to turn on but the amplitude of the signal on the ZCD pin is
smaller than the arming threshold for some reason (e.g. a heavy damping of drain
oscillations, like in some single-stage PFC topologies, or when a turn-off snubber is used),
MOSFET turn-on cannot be triggered. This case is identical to what happens at startup: at
the end of the next oscillator cycle the MOSFET is turned on, and a new switching cycle
takes place after skipping no more than one oscillator cycle.
The operation described so far does not consider the blanking time TBLANK after MOSFET
turn-off, and actually TBLANK does not come into play as long as the following condition is
met:
Equation 3
where D is the MOSFET duty cycle. If this condition is not met, nothing changes
substantially: the time during which MOSFET turn-on is inhibited is extended beyond Tosc by
a fraction of TBLANK. As a consequence, the maximum switching frequency is a little lower
than the programmed value fosc and valley-skipping mode may take place slightly earlier
than expected. However this is quite unusual: setting fosc = 150 kHz, the phenomenon can
be observed at duty cycles higher than 60%. See Section 5.11 for further implications of
TBLANK.
If the voltage on the COMP pin (9) saturates high, which reveals an open control loop, an
internal pull-up keeps the ZCD pin close to 2 V during MOSFET OFF-time to prevent noise
from false triggering the detection block. When this pull-up is active, the ZCD pin may not be
able to go below the triggering threshold, which would stop the converter. To allow auto-
restart operation, while ensuring minimum operating frequency in these conditions, the
oscillator frequency that retriggers MOSFET turn-on is that of the external oscillator divided
by 128. Additionally, to prevent malfunction at converter startup, the pull-up is disabled
during the initial soft-start (see Section 5.10). However, to ensure a correct startup, at the
end of the soft-start phase, the output voltage of the converter must meet the condition:
Equation 4
where Ns is the turn number of the secondary winding, Naux the turn number of the
auxiliary winding, and IZCD the maximum pull-up current (130 μA).
Application information L6566A
22/52 Doc ID 13794 Rev 4
The operation described so far under different operating conditions for the converter is
illustrated in the timing diagrams of Figure 10.
If the FF option is selected, the operation is exactly equal to that of a standard current-mode
PWM controller. It works at a frequency fsw = fosc; both DCM and CCM transformer
operations are possible, depending on the operating conditions (input voltage and output
load) and on the design of the power stage. The MOSFET is turned on at the beginning of
each oscillator cycle and is turned off as the voltage on the current sense pin reaches an
internal reference set by the line feedforward block. The maximum duty cycle is limited at
70% minimum. The signal on the ZCD pin in this case is used only for detecting feedback
loop failures (see Section 5.11).
Figure 10. Operation of ZCD, triggering and oscillator blocks (QR option active)
L6566A Application information
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5.3 Burst-mode operation at no load or very light load
When the voltage at the COMP pin (9) falls 20 mV below a threshold fixed internally at a
value, VCOMPBM, depending on the selected operating mode, the L6566A is disabled with
the MOSFET kept in OFF-state and its consumption reduced at a lower value to minimize
Vcc capacitor discharge.
The control voltage now increases as a result of the feedback reaction to the energy delivery
stop (the output voltage is slowly decaying), the threshold is exceeded and the device
restarts switching again. In this way the converter works in burst-mode with a nearly
constant peak current defined by the internal disable level. A load decreases and then
causes a frequency reduction, which can go down even to a few hundred hertz, therefore
minimizing all frequency-related losses and making it easier to comply with energy saving
regulations. This kind of operation, shown in the timing diagrams of Figure 11 along with the
others previously described, is noise-free since the peak current is low.
If it is necessary to decrease the intervention threshold of the burst-mode operation, this can
be done by adding a small DC offset on the current sense pin as shown in Figure 12.
Note: The offset reduces the available dynamics of the current signal; thereby, the value of the
sense resistor must be determined taking this offset into account.
Figure 11. Load-dependent operating modes: timing diagrams
Application information L6566A
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Figure 12. Addition of an offset to the current sense lowers the burst-mode
operation threshold
5.4 Adaptive UVLO
A major problem when optimizing a converter for minimum no-load consumption is that the
voltage generated by the auxiliary winding under these conditions falls considerably as
compared even to few mA load. This very often causes the supply voltage Vcc of the control
IC to drop and go below the UVLO threshold so that the operation becomes intermittent,
which is undesired. Furthermore, this must be traded off against the need of generating a
voltage not exceeding the maximum allowed by the control IC at full load.
To help the designer overcome this problem, the device, besides reducing its own
consumption during burst-mode operation, also features a proprietary adaptive UVLO
function. It consists of shifting the UVLO threshold downwards at light load, namely when
the voltage at the COMP pin falls below a threshold V COMPO internally fixed (see
Section 5.8), so as to have more headroom. To prevent any malfunction during transients
from minimum to maximum load, the normal (higher) UVLO threshold is re-established
when the voltage at the COMP pin exceeds V COMPL (see Section 5.8) and Vcc has
exceeded the normal UVLO threshold (see Figure 13). The normal UVLO threshold ensures
that at full load the MOSFET is driven with a proper gate-to-source voltage.
Figure 13. Adaptive UVLO block
L6566A Application information
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5.5 PWM control block
The device is specific to secondary feedback. Typically, there is a TL431 on the secondary
side and an optocoupler that transfers output voltage information to the PWM control on the
primary side, crossing the isolation barrier. The PWM control input (pin 9, COMP) is driven
directly by the phototransistor’s collector (the emitter is grounded to GND) to modulate the
duty cycle (Figure 14, left-hand side circuit).
In applications where a tight output regulation is not required, it is possible to use a primary-
sensing feedback technique. In this approach the voltage generated by the self-supply
winding is sensed and regulated. This solution, shown in Figure 14, right-hand side circuit,
is cheaper because no optocoupler or secondary reference is needed, but output voltage
regulation, especially as a result of load changes, is quite poor. Ideally, the voltage
generated by the self-supply winding and the output voltage should be related by the
Naux/Ns turn ratio only. In fact, numerous non-idealities, mainly transformer parasitics,
cause the actual ratio to deviate from the ideal one. Line regulation is quite good, in the
range of ± 2%, whereas load regulation is about ± 5% and output voltage tolerance is in the
range of ±10%.
The dynamic of the pin is in the 2.5 to 5 V range. The voltage at the pin is clamped
downwards at about 2 V. If the clamp is externally overridden and the voltage on the pin is
pulled below 1.4 V, the L6566A shuts down. This condition is latched as long as the device
is supplied. While the device is disabled, however, no energy is coming from the self-supply
circuit, therefore the voltage on the Vcc capacitor decays and crosses the UVLO threshold
after some time, which clears the latch and lets the HV generator restart. This function is
intended for an externally controlled burst-mode operation at light load with a reduced
output voltage, a technique typically used in multi-output SMPS, such as those for CRT TVs
or monitors (see the timing diagram Figure 15).
Figure 14. Possible feedback configurations that can be used with the L6566A
Application information L6566A
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Figure 15. Externally controlled burst-mode operation by driving the COMP pin:
timing diagram
5.6 PWM comparator, PWM latch and voltage feedforward blocks
The PWM comparator senses the voltage across the current sense resistor Rs and, by
comparing it to the programming signal delivered by the feedforward block, determines the
exact instant when the external MOSFET must be switched off. Its output resets the PWM
latch, previously set by the oscillator or the ZCD triggering block, which asserts the gate-
driver output low. The use of PWM latch avoids spurious switching of the MOSFET that may
result from the noise generated (“double-pulse suppression”).
Cycle-by-cycle current limitation is realized with a second comparator (OCP comparator)
that also senses the voltage across the current sense resistor Rs and compares this voltage
to a reference value VCSX. Its output is OR-ed with that of the PWM comparator (see the
circuit schematic in Figure 17). In this way , if the programming signal delivered by the
feedforward block and sent to the PWM comparator exceeds VCSX, it is the OCP comparator
that first resets the PWM latch instead of the PWM comparator. The value of Vcsx, thereby,
determines the overcurrent setpoint along with the sense resistor Rs.
The power that QR flyback converters with a fixed overcurrent setpoint (like fixed-frequency
systems) are able to deliver changes considerably with the input voltage. Obviously, this is
not a problem if the flyback converter runs off a fixed voltage bus generated by the PFC pre-
regulator; however, with a tracking boost PFC (a “boost follower” PFC), the regulated output
voltage at maximum mains voltage can be even twice the value at minimum mains voltage.
In this case the issue remains, although it is not as great as without PFC and wide-range
mains. With a 1: 2 voltage change, the maximum transferable power at maximum line can
