L6565D ,QUASI-RESONANT SMPS CONTROLLERfeatures a special function that automatically lowers the operating frequency still main-taining th ..
L6565DTR ,QUASI-RESONANT SMPS CONTROLLERL6565QUASI-RESONANT SMPS CONTROLLER■ QUASI-RESONANT (QR) ZERO-VOLTAGE-SWITCHING (ZVS) TOPOLOGY■ LIN ..
L6565N ,QUASI-RESONANT SMPS CONTROLLERL6565QUASI-RESONANT SMPS CONTROLLER■ QUASI-RESONANT (QR) ZERO-VOLTAGE-SWITCHING (ZVS) TOPOLOGY■ LIN ..
L6565N ,QUASI-RESONANT SMPS CONTROLLERBLOCK DIAGRAMCOMPVFF231INV-LINE VOLTAGEFEEDFORWARD+40K42.5VCS2 VVOLTAGE 5pF- + - +REGULATOR8 VCCHic ..
L6566A ,Multi-mode controller for SMPS with PFC front-endblock diagram 7Figure 3. Pin connection (through top view) . . . . 8Figure 4. Multi-mode ..
L6566ATR ,Multi-mode controller for SMPS with PFC front-endElectrical characteristics . . . . 115 Application information . . . . . 155.1 High-volta ..
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L6565D-L6565N
QUASI-RESONANT SMPS CONTROLLER
1/17
L6565January 2003 QUASI-RESONANT (QR) ZERO-VOLTAGE-
SWITCHING (ZVS) TOPOLOGY LINE FEED FORWARD TO DELIVER
CONSTANT POWER vs. MAINS CHANGE FREQUENCY FOLDBACK FOR OPTIMUM
STANDBY EFFICIENCY PULSE-BY-PULSE & HICCUP-MODE OCP ULTRA-LOW START-UP (< 70μA) AND
QUIESCENT CURRENT (< 3.5mA) DISABLE FUNCTION (ON/OFF CONTROL) 1% PRECISION (@ Tj = 25°C) INTERNAL
REFERENCE VOLTAGE ±400mA TOTEM POLE GATE DRIVER WITH
UVLO PULL-DOWN BLUE ANGEL, ENERGY STAR, ENERGY
2000 COMPLIANT
APPLICATIONS TV/MONITOR SMPS AC-DC ADAPTERS/CHARGERS DIGITAL CONSUMER PRINTERS, FAX MACHINES,
PHOTOCOPIERS AND SCANNERS
DESCRIPTIONThe L6565 is a current-mode primary controller IC,
specifically designed to build offline Quasi-resonant
ZVS (Zero Voltage Switching at switch turn-on) fly-
back converters.
Quasi-resonant operation is achieved by means of a
transformer demagnetization sensing input that trig-
gers MOSFET's turn-on.
QUASI-RESONANT SMPS CONTROLLER
BLOCK DIAGRAM
L6565 2/17
DESCRIPTION (continued)Converter's power capability variations with the mains voltage are compensated by line voltage feedforward.
At light load the device features a special function that automatically lowers the operating frequency still main-
taining the operation as close to ZVS as possible. In addition to very low start-up and quiescent currents, this
feature helps keep low the consumption from the mains at light load and be Blue Angel and Energy Star com-
pliant.
The IC includes also a disable function, an on-chip filter on current sense, an error amplifier with a precise ref-
erence voltage for primary regulation and an effective two-level overcurrent protection.
PIN CONNECTION (Top view, Minidip and SO8)
PIN DESCRIPTION
3/17
L6565
THERMAL DATA
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTCS (Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
L6565 4/17
(1)Parameters guaranteed by design, not tested in production.
ELECTRICAL CHARACTERISTCS (continued)(Tj = -25 to 125°C, VCC = 12V, Co = 1nF; unless otherwise specified)
5/17
L6565
Figure 1. Supply current vs. Supply voltage
Figure 2. Start-up & UVLO vs. Temperature
Figure 3. Feedback reference vs. Temperature
Figure 4. Line feedforward characteristics
Figure 5. Pin 2 (COMP) V-I characteristics
Figure 6. ZCD blanking time vs. COMP voltage
L6565 6/17
Figure 7. Gate-drive output saturation
Figure 8. Gate-drive output saturation
Figure 9. IC consumption vs. temperature
Figure 10. Zener voltage at Vcc pin vs. Tj
Figure 11. Start-up timer period vs. Tj
7/17
L6565
APPLICATION INFORMATIONQuasi-resonant operation in offline flyback converters lies in synchronizing MOSFET's turn-on to the transform-
er's demagnetization. Detecting the resulting negative-going edge of the voltage across any winding of the
transformer can do this. The L6565 is provided with a dedicated pin that allows doing the job with a very simple
interface, just one resistor.
Variable frequency operation - as a result of different operating conditions in terms of input voltage and output
current - is inherent in such functionality. The system always works close to the boundary between DCM (Dis-
continuous Conduction Mode) and CCM (Continuous Conduction Mode) operation of the transformer. The op-
eration is then identical to that of the so-called self-oscillating or Ringing Choke Converter (RCC).
Detailed Device DescriptionInternal Supply Block (see fig. 12)
A linear voltage regulator supplied by Vcc (pin 8) generates an internal 7V rail used for supplying the entire IC,
except for the gate driver that is supplied directly from Vcc. In addition, a bandgap circuit generates a precise
internal reference (2.5V±1% @ 25°C) used by the control loop to ensure a good regulation with primary feed-
back technique.
In figure 12 it is also shown the undervoltage lockout (UVLO) comparator with hysteresis used to enable the
chip as long as the Vcc voltage is high enough to ensure a reliable operation.
Figure 12. L6565 internal supply block
L6565 8/17
Zero Current Detection and Triggering Block (see fig. 13):
The Zero Current Detection (ZCD) block switches on the external MOSFET if a negative-going edge falling be-
low 1.6 V is applied to the input (pin 5, ZCD). However, to ensure high noise immunity, the triggering block must
be armed first: prior to falling below 1.6V, the voltage on pin 5 must experience a positive-going edge exceeding
2.1 V.
This feature is typically used to detect transformer demagnetization for QR operation, where the signal for the
ZCD input is obtained from the transformer's auxiliary winding used also to supply the IC. Alternatively, this can
be used to synchronize MOSFET's turn-on to the negative-going edge of an external clock signal, in case the
device is not required to work in QR mode but as a standard PWM controller in a synchronized system (e.g.
monitor SMPS).
The triggering block is blanked for a certain time after the MOSFET has been turned off. This has two goals:
first, to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the
ZCD circuit erroneously; second, to realize the Frequency Foldback function (see the relevant description).
Figure 13. Zero Current Detection and Triggering Block; Disable and Frequency Foldback BlocksA circuit is needed that turns on the external MOSFET at start-up since no signal is coming from the ZCD pin.
This is realized with an internal starter, which forces the driver to deliver a pulse to the gate of the MOSFET.
To minimize the external interface with the synchronization source (either the auxiliary winding or an external
clock), the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal dia-
gram of the ZCD block of figure 13. The upper clamp is typically located at 5.2 V, while the lower clamp is at
one VBE above ground. The interface will then be made by just one resistor that has to limit the current sourced
by and sunk from the pin within the rated capability of the internal clamps.
Disable Block (see fig. 13):
The ZCD pin is used also to activate the Disable Block. If the voltage on the pin is taken below 150 mV the de-
vice will be shut down. To do so, it is necessary to override the source capability (10 mA max.) of the internal
lower clamp. While in disable, the current consumption of the IC will be reduced. To re-enable device operation,
the pull-down on the pin must be released.
Frequency Foldback Block (see fig. 13):
To prevent the switching frequency from reaching too high values, which is a typical drawback of QR operation,
9/17
L6565the L6565 puts a limit on the minimum OFF-time of the switch. This is done by blanking the triggering block of
the ZCD circuit as mentioned before. The duration of the blanking time (3.5μs min.) is a function of the error
amplifier output VCOMP, as shown in the diagram of figure 6.
If the load current and the input voltage are such that the switch OFF-time falls below the minimum blanking
time of 3.5μs, the system will enter the "Frequency Foldback" mode, a sort of "ringing cycle skipping" illustrated
schematically in figure 14.
Figure 14. Frequency foldback: ringing cycle skipping as the load is progressively reducedIn this mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that
the OFF-time of the MOSFET is allowed to change with discrete steps (2·Tv), while the OFF-time needed for
cycle-by-cycle energy balance may fall in between. Thus one or more longer switching cycles will be compen-
sated by one or more shorter ones and vice versa. However, this mechanism is absolutely normal and there is
no appreciable effect on the performance of the converter or on its output voltage.
Figure 15. Frequency Foldback: qualitative
frequency dependence on power
throughputFurther load reductions involve lower values for
VCOMP, which increases the blanking time. There-
fore, more and more ringing cycles will be skipped.
When the load is low enough, so many ringing cycles
need to be skipped that their amplitude becomes
very small and they can no longer trigger the ZCD cir-
cuit. In that case the internal starter of the IC will be
activated, resulting in burst-mode operation: a series
of few switching cycles spaced out by long periods
where the MOSFET is in OFF state.
Voltage Feedforward block (see fig. 17b):
The power that QR flyback converters with a fixed
overcurrent setpoint (like fixed-frequency systems)
are able to deliver changes with the input voltage
considerably. With wide-range mains, at maximum
line it can be more than twice the value at minimum
line, as shown by the upper curve in the diagram of
figure 16. The L6565 has the Line Feedforward func-
tion available to solve this issue.
Figure 16. Typical power capability change vs.
input voltage in ZVS QR flyback
converters
