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L6374DP ,INDUSTRIAL QUAD LINE DRIVERABSOLUTE MAXIMUM RATINGSSymbol Pin Parameter Value UnitVS 1 Supply Voltage (t < 10ms) 50 VWSupply V ..
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L6374FP ,INDUSTRIAL QUAD LINE DRIVERTHERMAL CHARACTERISTICSbottom side of an horizontal PCB (worst case).Rth j-pinsRth j-amb2POWERDIP. ..
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L6374DP-L6374FP
INDUSTRIAL QUAD LINE DRIVER
L6374INDUSTRIAL QUAD LINE DRIVER
ADVANCE DATAFOUR INDEPENDENT LINE DRIVERS WITH
100 mA UP TO 35V OUTPUTS
INPUT SIGNALS BETWEEN -7V AND +35V,
WITH PRESETTABLE THRESHOLD
PUSH-PULL OUTPUTS WITH THREE STATE
CONTROL AND TRUE ZERO CURRENT BE-
TWEEN VS AND GROUND
CURRENT LIMITING ON EACH OUTPUT EF-
FECTIVE IN THE FULL "GROUND TO VS"
OUTPUT VOLTAGE RANGE
OUTPUT VOLTAGE CLAMP TO VS AND TO
GROUND
OVERTEMPERATURE AND UNDERVOL-
TAGE PROTECTIONS
DIAGNOSTIC FOR OVERTEMPERATURE,
UNDERVOLTAGE AND OVERCURRENT
PRESETTABLE DELAY FOR OVERCUR-
RENT DIAGNOSTIC
HIGH SPEED OPERATION: UP TO 300kHz
WITH 35V SWING
DESCRIPTIONThe L6374 is especially designed to be used as a
line driver in industrial control systems based on
the 24V signal levels (IEC1131, 24VDC).
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTION (Top view)
L6374
ELECTRICAL CHARACTERISTICS (VS = 24V; Tj = -25 to 125°C; unless otherwise specified.)
DC OPERATION
AC OPERATION (VS = 10.8 to 35V; Tj = -25 to 125°C; Iout = 100mA; unless otherwise specified; see
switching waveforms diagrams)
L6374
THERMAL CHARACTERISTICSRth j-pins
POWERDIP. The thermal resistance is referredto the thermal path from the dissipating region
on the top surface of the silicon chip, to the
points along the four central pins of the pack-
age, at a distance of 1.5 mm away from the
stand-offs.
SO. Similarly, the reference point is the kneeon the four central pins, where the pins are up-
wardly bent and the soldering joint with the
PCB footprint can be made.
Rth j-amb1
If a dissipating surface, thick at least 35 μm,
and with a surface similar or bigger than the
one shown, is created making use of the
printed circuit.
Such heatsinking surface is considered on the
bottom side of an horizontal PCB (worst case).
Rth j-amb2
If the power dissipating pins (the four central
ones), as well as the others, have a minimum
thermal connection with the external world
(very thin strips only) so that the dissipation
takes place through still air and through the
PCB itself.
It is the same situation of point above, without
any heatsinking surface created on purpose on
the board.
Additional data for the PowerDip package can be
found in:
Application Note 9030:
Thermal Characteristics of the PowerDip
20,24 Packages Soldered on 1,2,3 oz.
Copper PCB
THERMAL DATA
Figure 1: Printed Heatsink
L6374
OVERTEMPERATURE PROTECTION (OVT)If the chip temperature exceeds Th (measured in
a central position in the chip) the chip deactivates
itself.
The following actions are taken:
- all the output stages are forced in the "three
state" condition, i.e. are disconnected from
the output pins; only the clamping diodes at
the outputs remain active;
- the signal Diag is activated (active low).
Normal operation is resumed as soon as (typically
after some seconds) the chip temperature moni-
tored goes back below Th -HT.
The different upper and lower thresholds with
hysteretic behavior, assure that no intermittent
conditions can be generated.
UNDERVOLTAGE PROTECTION (UV)The supply voltage is expected to range from 11V
to 35V, even if its reference value is considered to
be 24V.
In this range the L6374 operates correctly.
Below 10.8V the overall system has to be consid-
ered not reliable.
Consequently the supply voltage is monitored
continuously and a signal, called UV, is internally
generated and used.
The signal is "on" as long as the supply voltage
does not reach the upper internal threshold of the
Vs comparator (called Vsh). The UV signal disap-
pears above Vsh.
Once the UV signal has been removed, the sup-
ply voltage must decrease below the lower
threshold (i.e. below Vsh -Hys1) before it is turned
on again.
The hysteresis Hys1 is provided to prevent inter-
mittent operation of the device at low supply volt-
ages that may have a superimposed ripple
around the average value.
The UV signal inhibits the outputs, putting them in
three-state, but has no effect on the creation of
the reference voltages for the internal compara-
tors, nor on the continuous operation of the
charge-pump circuits.
DIAGNOSTIC LOGICThe situations that are monitored and signalled
with the Diag output pin are:
- current limit (OVC) in action; there are 8 indi-
vidual current limiting circuits, two per each
output, i.e. one per every output transistor;
they limit the current that can be either sour-
ced or sunk from each output, to a typical
value of 150mA, equal for all of them;
- undervoltage protection (UV);
- overtemperature protection (OVP);
The diagnostic signal is transmitted via an open
drain output (for ease of wired-or connection of
several such signals) and a low level represents
the presence of at least one of the monitored con-
ditions, mentioned above.
PROGRAMMABLE DELAYThe current limiting circuits can be requested to
perform even in absence of a real fault condition,
for a short period, if the load is of capacitive na-
ture or if it is a filament lamp (that exhibits a very
low resistance during the initial heating phase).
To avoid the forwarding of misleading, short diag-
nostic pulses in coincidence with the intervention
of the current limiting circuits when operating on
capacitive loads, a delay of about 5μs is inserted
on the signal path, between the "OR" of the cur-
rent limit signals and its use as external diagnostic.
It takes about 1μs to charge (or discharge) by
24V a capacitor of 5nF with a current of 120mA .
To implement longer delays (from the intervention
of one of the current limiting circuits to the activa-
tion of the diagnostic) an external capacitor can
be connected between pin C3 and ground (pin C3
is otherwise left open).
The delay shall then be determined by the ratio of
about 10 pF/μs, using the value of the capaci-
tance connected to the pin.
ANALOG INPUTS (I1,I2,I3,I4)The input stage of each channel is a high im-
pedence comparator with built-in hysteresis
(200mV) for high noise immunity. Each compara-
tor has one input connected to all the others and
tied to a common pin Ref (Pin 11). If this pin is left
floating an internal precise band gap voltage ref-
erence (1.25V) is applied, otherwise these inputs
can be externally programmed by connecting an
external voltage source (from 0 to 5V) and the
current on this pin is internally limited to ±20μA.
The other input pin of each comparator can swing
from -7 to 35V.
For this reason it has been implemented the
structure shown in Figure 2 and the device can
also be used as line receiver.
When the input voltage is negative, the current is
internally limited by a 15kΩ resistor as shown in
Figure 2. High and low input thresholds can be
obtained by adding and subtracting half of the
hysteresis to the voltage of pin Ref (see Figure 3).
Figure 2: Equivalent input circuit
L6374
