L6258 Fast Delivery |IC PHOENIX CO.,LIMITED

L6258 ,PWM CONTROLLEDL6258®PWM CONTROLLED - HIGH CURRENTDMOS UNIVERSAL MOTOR DRIVERABLE TO DRIVE BOTH WINDINGS OF A BI-P ..
L6258 ,PWM CONTROLLEDABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitVs Supply Voltage 36 VVCC Logic Supply Voltage 7 ..
L6258E ,PWM CONTROLLEDL6258EPWM CONTROLLED - HIGH CURRENTDMOS UNIVERSAL MOTOR DRIVER■ ABLE TO DRIVE BOTH WINDINGS OF A BI ..
L6258E ,PWM CONTROLLEDABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Supply Voltage 45 VsV Logic Supply Voltage 7 V ..
L6258EA ,PWM CONTROLLED
L6258EP ,PWM-controlled, high-current DMOS universal motor driver
LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC331632M-70 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC338128M-70 ,1 MEG (131072 words x 8 bit) pseudo-SRAMFeatures. 131072 words x 8 bits configuration. CE access time, COE access time, cycle time, operati ..
LC338128M-80 ,1 MEG (131072 words x 8 bit) pseudo-SRAMPin AssignmentAuA1:A7A5"A:"A2Al"1/0:1/021/0:END 1DIP32, SOP32VccA15Ax:1/051/07TADSvns1/04Top viewAu ..
LC33832M-10 ,256K (32768word x 8bit) Pseudo-SRAMFeatures3133-DIP28• 32768 words · 8 bits configuration• Single 5 V ±10% power supply[LC33832S, SL]• ..
LC33832M-70 ,256K (32768word x 8bit) Pseudo-SRAMOrdering number : EN4430CCMOS LSILC33832P, S, M, PL, SL, ML-70/80/10256 K (32768 words · 8 bits) Ps ..

L6258
PWM CONTROLLED
L6258
PWM CONTROLLED - HIGH CURRENT
DMOS UNIVERSAL MOTOR DRIVER
ABLE TO DRIVE BOTH WINDINGS OF A BI-
POLAR STEPPER MOTOR OR TWO DC MO-
TORS
OUTPUT CURRENT UP TO 1.2A EACH
WINDING
WIDE VOLTAGE RANGE: 12V TO 34V
FOUR QUADRANT CURRENT CONTROL,
IDEAL FOR MICROSTEPPING AND DC MO-
TOR CONTROL
PRECISION PWM CONTROL
NO NEED FOR RECIRCULATION DIODES
TTL/CMOS COMPATIBLE INPUTS
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOWN
DESCRIPTION
L6258 is a dual full bridge for motor control appli-
cations realized in BCD technology, with the ca-
pability of driving both windings of a bipolar step-
per motor or bidirectionally control two DC
motors.
L6258 and a few external components form a
complete control and drive circuit. It has high effi-
ciency phase shift chopping that allows a very low
current ripple at the lowest current control levels,
and makes this device ideal for steppers as well
as for DC motors.
The power stage is a dual DMOS full bridge capa-
ble of sustaining up to 34V, and includes the di-
odes for current recirculation.
The output current capability is 1.2A per winding
in continuous mode, with peak start-up current up
to 1.5A.
A thermal protection circuitry disables the outputs
if the chip temperature exceeds the safe limits.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
PIN CONNECTION (Top view)
L6258
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PIN FUNCTIONS
Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together.
L6258
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THERMAL CHARACTERISTICS
L6258
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ELECTRICAL CHARACTERISTICS
(VS = 34V; VCC = 5V; Tj = 25°; unless otherwise specified.)
Note 1: This is true for all the logic inputs except the disable input.
(*) Chopping frequency is twice fosc value.
THERMAL DATA
(*) Depending on board and soldering.
L6258
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FUNCTIONAL DESCRIPTION
The circuit is intended to drive both windings of a
bipolar stepper motor or two DC motors.
The current control is generated through a switch
mode regulation.
With this system the direction and the amplitude
of the load current are depending on the relation
of phase and duty cycle between the two outputs
of the current control loop.
The L6258 power stage is composed by power
DMOS in bridge configuration as it is shown in fig-
ure 1, where the bridge outputs OUT_A and
OUT_B are driven to Vs with an high level at the
inputs IN_A and IN_B while are driven to ground
with a low level at the same inputs .
The zero current condition is obtained by driving
the two half bridge using signals IN_A and IN_B
with the same phase and 50% of duty cycle.
In this case the outputs of the two half bridges are
continuously switched between power supply (Vs)
and ground, but keeping the differential voltage
across the load equal to zero.
In figure 1A is shown the timing diagram of the
two outputs and the load current for this working
condition.
Following we consider positive the current flowing
into the load with a direction from OUT_A to
OUT_B, while we consider negative the current
flowing into load with a direction from OUT_B to
OUT_A.
Now just increasing the duty cycle of the IN_A
signal and decreasing the duty cycle of IN_B sig-
nal we drive positive current into the load.
In this way the two outputs are not in phase, and
the current can flow into the load trough the di-
agonal bridge formed by T1 and T4 when the out-
put OUT_A is driven to Vs and the output OUT_B
is driven to ground, while there will be a current
recirculation into the higher side of the bridge,
through T1 and T2, when both the outputs are at
Vs and a current recirculation into the lower side
of the bridge, through T3 and T4, when both the
outputs are connected to ground.
Since the voltage applied to the load for recircula-
tion is low, the resulting current discharge time
constant is higher than the current charging time
constant during the period in which the current
flows into the load through the diagonal bridge
formed by T1 and T4. In this way the load current
will be positive with an average amplitude de-
pending on the difference in duty cycle of the two
driving signals.
In figure 1B is shown the timing diagram in the
case of positive load current
On the contrary, if we want to drive negative cur-
rent into the load is necessary to decrease the
duty cycle of the IN_A signal and increase the
duty cycle of the IN_B signal. In this way we ob-
tain a phase shift between the two outputs such
to have current flowing into the diagonal bridge
formed by T2 and T3 when the output OUT_A is
driven to ground and output OUT_B is driven to
Vs, while we will have the same current recircula-
tion conditions of the previous case when both
the outputs are driven to Vs or to ground.
So, in this case the load current will be negative
with an average amplitude always depending by
the difference in duty cycle of the two driving sig-
nals.
In figure 1C is shown the timing diagram in the
case of negative load current .
Figure 2 shows the device block diagram of the
complete current control loop.
Reference Voltage
The voltage applied to VREF pin is the reference
for the internal DAC and, together with the sense
resistor value, defines the maximum current into
the motor winding according to the following rela-
tion:
IMAX = 0.5 ⋅ VREF = 1 ⋅ VREF
where Rs = sense resistor value
L6258
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Figure 1. Power Bridge Configuration
L6258
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Input Logic (I0 - I1 - I2 - I3)
The current level in the motor winding is selected
according to this table:
Phase Input ( PH )
The logic level applied to this input determines
the direction of the current flowing in the winding
of the motor.
High level on the phase input causes the motor
current flowing from OUT_A to OUT_B through
the load.
Triangular Generator
This circuit generates the two triangular waves
TRI_0 and TRI_180 internally used to generate
the duty cycle variation of the signals driving the
output stage in bridge configuration.
The frequency of the triangular wave defines the
switching frequency of the output, and can be ad-
justed by changing the capacitor connected at
TR1_CAP pin :
Fref = K
where : K = 1.5 x 10-5
Figure 2. Current Control Loop Block Diagram
L6258
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Charge Pump Circuit
To ensure the correct driving of the high side driv-
ers a voltage higher than Vs is supplied on the
Vboot pin. This boostrap voltage is not needed for
the low side power DMOS transistors because
their sources terminals are grounded. To produce
this voltage a charge pump method is used. It is
made by using two external capacitors; one con-
nected to the internal oscillator (CP) and the other
(Cboot) to storage the overvoltage needed for the
driving the gates of the high side DMOS. The
value suggested for the capacitors are:
Current Control LOOP
The current control loop is a transconductance
amplifier working in PWM mode.
The motor current is a function of the pro-
grammed DAC voltage.
To keep under control the output current, the cur-
rent control modulates the duty cycle of the two
outputs OUT_A and OUT_B, and a sensing resis-
tor Rs is connected in series with the motor wind-
ing in order to produce a voltage feedback com-
pared with the programmed voltage of the DAC .
The duty cycle modulation of the two outputs is
generated comparing the voltage at the outputs of
the error amplifier, with the two triangular wave
references .
In order to drive the output bridge with the duty
cycle modulation explained before, the signals
driving each output ( OUTA & OUTB ) are gener-
ated by the use of the two comparators having as
reference two triangular wave signals Tri_0 and
Tri_180 of the same amplitude, the same average
value (in our case Vr), but with a 180° of phase
shift each other.
The two triangular wave references are respec-
tively applied to the inverting input of the first
comparator and to the non inverting input of the
second comparator .
The other two inputs of the comparators are con-
nected together to the error amplifier output volt-
age resulting by the difference between the pro-
grammed DAC. The reset of the comparison
between the mentioned signals is shown in fig. 3.
Figure 3. Output comparator waveforms
L6258
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In the case of VDAC equal to zero, the transcon-
ductance loop is balanced at the value of Vr, so
the outputs of the two comparators are signals
having the same phase and 50% of duty cycle .
As we have already mentioned, in this saturation,
the two outputs OUT_A and OUT_B are simulta-
neously driven from Vs to ground ; and the differ-
ential voltage across the load in this case is zero
and no current flows in the motor winding.
With a positive differential voltage on VDAC (see
Fig 2, the transconductance loop will be positively
unbalanced respected Vr.
In this case being the error amplifier output volt-
age greater than Vr, the output of the first compa-
rator is a square wave with a duty cycle higher
than 50%, while the output of the second compa-
rator is a square wave with a duty cycle lower
than 50%.
The variation in duty cycle obtained at the outputs
of the two comparators is the same, but one is
positive and the other is negative with respect to
the 50% level.
The two driving signals, generated in this case,
drive the two outputs in such a way to have
switched current flowing from OUT_A through the
motor winding to OUT_B.
With a negative differential voltage VDAC, the tran-
sconductance loop will be negatively unbalanced
respected Vr.
In this case the output of the first comparator is a
square wave with a duty cycle lower than 50%,
while the output of the second comparator is a
square wave with a duty cycle higher than 50%.
The variation in the duty cycle obtained at the out-
puts of the two comparators is always of the
same.
The two driving signals, generated in this case,
drive the the two outputs in order to have the
switched current flowing from OUT_B through the
motor winding to OUT_A.
Current Control Loop Compensation
In order to have a flexible system able to drive
motors with different electrical characteristics, the
non inverting input and the output of the error am-
plifier ( EA_OUT ) are available.
Connecting at these pins an external RC com-
pensation network it is possible to adjust the gain
and the bandwidth of the current control loop.
PWM CURRENT CONTROL LOOP
Open Loop Transfer Function Analysis
Block diagram : refer to Fig. 2.
Application data:
these data refer to a typical application, and will
be used as an example during the analysis of the
stability of the current control loop.
The block diagram shows the schematics of the
L6258 internal current control loop working in
PWM mode; the current into the load is a function
of the input control voltage VDAC , and the relation
between the two variables is given by the follow-
ing formula:
Iload ⋅ RS ⋅ GS = VDAC ⋅ Gin
Iload ⋅ RS ⋅ 1 = VDAC ⋅ 1
Iload = VDAC ⋅ Rb
Ra ⋅ RS = 0.5 ⋅ VDAC (A)
where:
VDAC is the control voltage defining the
load current value
Gin is the gain of the input transcon-
ductance amplifier ( 1/Ra ) is the gain of the sense transcon-
ductance amplifier ( 1/Rb ) is the resistor connected in series
to the output to sense the load
current
In this configuration the input voltage is compared
with the feedback voltage coming from the sense
resistor, then the difference between this two sig-
nals is amplified by the error amplifier in order to
have an error signal controlling the duty cycle of
the output stage keeping the load current under
control.
It is clear that to have a good performance of the
current control loop, the error amplifier must have
an high DC gain and a large bandwidth .
Gain and bandwidth must be chosen depending
on many parameters of the application, like the
characteristics of the load, power supply etc...,
and most important is the stability of the system
that must always be guaranteed.
To have a very flexible system and to have the
possibility to adapt the system to any application,
the error amplifier must be compensated using an
L6258
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Partno	Mfg	Dc	Qty	Available	Descript
L6258	STM	N/a	401	avai	PWM CONTROLLED
L6258	ST	N/a	620	avai	PWM CONTROLLED