L6238 Fast Delivery |IC PHOENIX CO.,LIMITED

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L6238
SENSORLESS SPINDLE MOTOR CONTROLLER
L6238
SENSORLESS SPINDLE MOTOR CONTROLLER
PRODUCT PREVIEW
2.5A, THREE-PHASE OUTPUT DRIVE
PRECISION DIGITAL PLL
FULLY-INTEGRATEDALIGN+ GO
START-UP ALGORITHM
DIGITAL BEMF PROCESSING
MASTER/SLAVE SYNCHRONIZATION
BIDIRECTIONAL SERIAL PORT
STAND ALONE OR EXT. DRIVER
SHOOT-THROUGH PROTECTION
DESCRIPTION
The L6238isa complete Three-Phase, D.C.
Brushless Spindle Motor Driver system. The de-
vice features both the Power and Control Sec-
tions and will operate Stand Alone,or can be
usedin Higher Power Applications with the addi-
tionofan external Linear Driver.
Start-Up can be achieved with the Fully-Inte-
grated Align+ GO Algorithm or may be se-
quenced manuallyfor User-Defined start-up algo-
rithms. Digital PLL provides high accuracy and the ca-
pabilityto do Master/Slave Synchronization for
Disk Array configurations.
Programmable functions include commutation
Timing Adjustment and Slew Rate Control for
peak efficiency and minimum noise.
Protective features include Stuck Rotor\Backward
Rotation Detection and Automatic Thermal Shut-
down.
BLOCK DIAGRAM
PLCC44
ORDERING NUMBER: L6238
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
BVdss OutputBrakdown Voltage 17 V
VPower Motor Supply Voltage 15 V
VLogic Logic Supply Voltage 7 V
VAnalog Analog Supply Voltage 15 V
Vin Input Voltage -0.3to7 V
Imdc Peak Motor Current (DC) 3 A
Impk Peak Motor Current (Pulsed:Ton= 5ms, d.c.= 10%) 5 A
Ptot Power Dissipationat Tamb= 50°C 2.5 W Storage and Junction Temperature -40to 150 °C
THERMAL DATA
Symbol Parameter Value Unit
Rth (j-pin) Thermal Resistance Junction-Pin 7 °C/W
Rth (j-amb) Thermal Resistance Junction-Ambient (Float.) 68 °C/W
PIN CONNECTION (Top view)
L6238
GENERAL DESCRIPTION
The L6238is an integrated circuit that will be
usedto commutate and speed controla 3-Phase,
8-pole, brushless, DC motor. The primary applica-
tionis for disk drive spindle motors. This I.C. has
the following features: Motor Hall Effect Sensors are required for
commutationor speed control. Timing informa-
tionis determined from the Bemf voltageof the
undriven motor terminal.
On-board Speed Control viaa Phase Locked
Loop that acceptsa once-per-rev reference
frequency and locks the motor to that fre-
quency. The L6238 can accomodatea wide
rangeof speeds.
The L6238 achieves Spindle Synchronization lockingtoa once-per-rev reference thatis
commonto multiple drives. The L6238 hasa
multiplexer that enhances the versatilityof the
controller. This first multiplexer selects either
internal feedback, (generated by the Bemfof
the motor),or external feedback (embedded
index). External P-Channel FET canbe connected the FET can be connectedto the FET
Bridgefor Higher Power Applications. this configuration, the internal DMOS drivers
are sequencedin full conduction state and the
external PFETis the linear control element. An
internal inverting buffer from the outputof the
OTA controls the conductionof the EXT PFET. internal Virtual Center Tapis usedif the
motor center tapis not connected.
The motor Current Limit can be setby an ex-
ternal resistor divider. Serial Portis included so that I/O can be
done witha minimumof pins. Key control and
status lines are also bonded outto achievea
Minimum Configuration without using the Serial
Port.
Programmable Functions include Phase
Switch Timing Optimization for motor effi-
ciency, Speed Lock Threshold, Auto-Startor Supervised Spinup, and output current lim-
iting gain.
Energy Recovery Mode for Head Retraction,
followedby Dynamic Braking Mode.
Logic signals are CMOS Compatible.
Stuck Rotor and Backward Rotation detection.
Automatic Thermal Shutdown with early warn-
ingbit availablein the statusregister
PIN FUNCTIONS Name I/O Function OUTPUTB I/O DMOS Half Bridge Output and InputBfor Bemf sensing. SPIN SENSE O Togglessat each Zero Crossingofthe Bemf. BRAKE DELAY I Energy Recovery time constant, definedby externalR-Cto ground.
4Rsense O Outputs A+B connectionsfor the Motor Current Sense Resistorto ground CHARGE PUMP2 I Negative Terminalof Pump Capacitor.7,
17,29,
39,40
GROUND I Ground terminals. CHARGE PUMP1 I Positive terminalof Pump Capacitor. CHARGE PUMP3 I Positive terminalof StorageCapacitor. OUTPUTA I/O DMOS Half Bridge Output and InputAfor Bemf sensing.
11,42 Vpower I Suppliesthe voltageforthe Power Section. Vanalog I 12V supply. SER PORT
DISABLE Inputfor tri-stating the serial port. SER DATA R/W I Selects Serial Data Reador Write Function. SER STROBE I Dtat Strobe Input. SER PORT CLK I Clockfor Serial Data Control. SER DATAI/O I/O Data stream Input/Outputfor Control/Status Registers. EXT/INT I Selectsthr Internal BEMF ZeroCrossingoran External Sourceas Feedback
Frequency forte PLL. FREF ENABLE I A zeroon thispin passes the PLL Fref signalto the Freq/phase detector.
L6238
ELECTRICAL CHARACTERISTICS (Referto the test circuit, unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
POWER SECTION
VPower Motor Supply 10.5 12 13.5 V
RDS(on) Output ON Resistance Tj =25°C= 125°C
0.25 0.33
Io(leak) Output Leakage Current 1 mA Body Diode Forward Drop Im= 2.0A 1.5 V
dVo/dt Output Slew Rate Rslew= 100KΩ 0.30 V/μs
Im(max) Motor Current Limit (Note1) Rs= 0.33Ω
Ilim Gain=0
Ilim Gain=1
TBD
TBD
TBD
TBD
A/V
A/V
Igt Gate Drivefor Ext. Power
DMOS
ILIMSET =5V
Ilim Gain=0
V33= 0V, V38=5V
5mA
Tsd Shut Down Temperature 150 180 °C
Thys Recovery Temperature
Hysteresis °C
Tew Early Warning Temperature Tsd-25 °C
Isnsin Current Sense Amp Input Bias
Current μA Current Sense Amp Voltage
3.8 4 4.2 V/V
PIN FUNCTIONS (continued) Name I/O Function RUN/BRAKE I Rising edgewill initiate start-up.A Braking rountineis started when this inputis
brought low. SEQ INCREMENT I A lowto high transitionon thispin increments the Output State Sequencer. SYSTEM CLK I Clock Frequencyfor the system timer/counters. EXT INDEX I External Sourceof Feedbackforthe PLL. PLL Fref I Reference Frequencyfor the PLL. LOCK O High when thePLLis phase_locked. Vlogic I Logic power supply. DETECTOR OUT O Outputof Frequency/Phase Detector. FILTERIN I Filter Input. FILTER COMP O Filter output and compensation. CSA INPUT I Inputtothe Current Sense Amplifier. Rsense O OutputC connectionfor the Motor Current Sense Resistorto ground. OUTPUTC I/O DMOS Half Bridge Output and InputCfor Bemf sensing. gm COMP I A seriesRC network toground thatdefines the compensationof the
Transconductance Loop. GATE DRIVE I/O Drives the Gateof the ExternalP Channel DMOS Driverfor Higher Power
Applications. This pin mustbe groundedifan external driverisnot used. I LIMIT SET I A voltage appliedto this pin,in conjunction withthe valueforthe external
Motor CurrentSensing resistor, defines the maximum Motor Current. CENTER TAP I Motor Center Tap usedfor differential BEMF sensing.Ifthe centertapofthe
Motorisnot brought out,a virtual centertapis integrated and availableat this
pin. SLEW RATE I A resistor connectedto thispin sets the Voltage Slew Rateofthe Output
Drivers.
L6238
ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
LOGIC SECTION
VinH
VinL
Input Voltage TBD
TBD
IinH
IinL
Input Current μA
VoutL
VoutH
Output Voltage Vsink= 2mA
Vsource= 2mA 4.5
0.5 V
Fsys System Clock Frequency 8 12 MHz
ton Clock ON Time 20 ns
toff Clock OFF Time 20 ns
SEQUENCE INCREMENT
tseq Time Between Rising Edges 1 μs
SERIAL PORT TIMINGNote: Cload(data I/O)= 50pF;
Fshift Clock Frequency 2 TBD MHz
tos Operating Set-up Time 50 ns
tsettle Enabling Settling Time 50 ns
tstrobe Strobe Pulse Width 40 ns
twait Disable Wait Time 40 ns
tds Data Setup Time 100 ns
tdh Data Hold Time 10 ns
tsd Strobeto Data Prop. Delay (*) 100 ns
tcd Clock toData Prop. Delay (*) 100 ns
tsd Data I/OActivation Delay (*) 100 ns
ttsd Data I/OTri State Delay 80 ns
twrs Writeto Read Set-up Time 50 ns
tscr Strobeto Clock Time
(Read Mode) ns
tcsw Clock toStrobe Time
(Write Mode) ns
PHASE LOCK LOOP SECTION
Tphse Static Phase Error 20 μs
BRAKE DELAY SECTION
Vchrg Capacitor Charge Voltage RT= 50K TBD 9.5 TBD V
Iout3 Source Current 0.5 mA
VThres Delay Timer Low Trip Threshold TBD 1.8 TBD V
CHARGE PUMP
Vout9 Storage Capacitor Output
Voltage V
Vleak Blocking Diode Leakage Current 10 μA
Fcp Charge Pump Frequency 300 KHz
(*) These parametersare afunctionof Cload.
L6238
FUNCTIONAL DESCRIPTION
1.0 INTRODUCTION
1.1 Typical Applicationa typical application, the L6238 will operatein
conjunction with the L6243 Voice Coil Driver as
shownin Fig.1. This configuration requiresa
minimum amountof external components while
providing complete stand-alone operation.
Figure1: StandAlone Configuration
L6238
1.2 Input Default States
Figure2 depicts the two possible input structures
for the logic inputs.Ifa particular pinis not used an application,it may either be connectedto
groundor VLOGICas required,or simply left un-
connected.If no connectionis made, the pinis
either pulled highor lowby internal constant cur-
rent generatorsas shown listingof the logic inputsis shown with the cor-
respondingdefault state.
1.3 Naming Convention orderto differentiatebetween the various types control and status signals, the following naming
conventionis used.
BOLD CAPITALS- Device pins.
Italics- Serial port control and status signals.
Three input signals forma special case. Referring figure3, the RUN/BRAKE input pin and the
Run/Brake control signal forma logical AND func-
tion, while OUTPUT ENABLE and Output Enable
forman OR function. The outputs signal names,
signals. Although not shown, SEQUENCE IN-
CREMENT and Sequence Increment also form OR function, with the resultant output signal
called Sequence Increment.
1.4 Modesof Operation
There are5 basic modesof operation. Tristate
When Output Enableis low, the output power
drivers are tristated. Start-Up
With Output Enable high, bringing Run/Brake
froma lowtoa high will energize the motor and
the system will be driven by the Fully-Integrated
StartUp Algorithm.A user-defined Start-Up Algo-
rithm, under controlofa MicroProcessor, can be
achieved viaa serial port and/or external control
pins. Run
Identified by the Lock signal, Run mode is
achieved when the motor speed (controlledby the
Internal PLL) reaches the nominal speed withina
predefined phase error. Park
When Run/Brakeis brought low, energyto park
the heads maybe derived from the rectified Bemf.
The energy recovery timeisa functionof the
Brake Delay Time Constant.In this state, the qui-
escent currentof the deviceis minimized (sleep
mode). Brake
After the Energy Recovery Time-Out, the devicein Brake, withall lower Driversin full conduc-
tion.
Duringa powerdown, the Park Modeis triggered,
followedbya Dynamic Brake.
There are two mutually exclusive conditions
Figure2: InputStructures
FUNCTION CONFIGURATION
PORT DIS
STROBE
PORT CLK
R/W
DATAI/O
EXT/INT
FREF ENABLE
LIN
OUTPUT ENABLE
RUN/BRAKE
SEQ INCR
SYS CLOCK
EXT INDEX
PLL FREF
PULL-UP
PULL-DOWN
PULL-UP
PULL-UP
PULL-UP
PULL-DOWN
PULL-DOWN
PULL-DOWN
PULL-DOWN
PULL-UP
PULL-DOWN
PULL-UP
PULL-UP
PULL-UP
Figure3: Input Logic
L6238
a)the spindleis stopped.
b)the systemis still runningata speed that
allowsfor resynchronization. orderto minimize the rampup time, the micro-
controller has the possibilityto:
check the SPIN SENSE pin, (which togglesat
the Bemf zero crossing frequency)
enable the powerto the motor based on the
previous information. Otherwise the uP mayis-
suea Brake command, followed by the start- procedure after the motor has stopped spin-
ning.
Brake
W/Mask
Hold& wait
for decision
Tri-state
W/Mask
Tri-state
W/Mask
RunBrk=1
OutEna=0
RunBrk=1
OutEna=1
OutEna=1
RunBrk=0
Run
W/Mask
Holdfor
”Align&Go”
RunBrk
OutEna
Power
on
Reset
OutEna
RunBrk
RunBrk
RunBrk=0
OutEna=0
SeqInc=X
Run
Wo/Mask
SeqInc=0
SeqInc=1
SeqInc=0
SeqInc=1
Action across
line increments
sequencer
Auto Start-up
Enabled Disabled
RunBrk=1
OutEna=0
RunBrk=1
OutEna=1
Holdfor
”Align&Go”
Start
”Align&Go”
Align= Seqncr.
[Align
Phase
StkRtr
[Align
to
Phase
Align0o=
Align
RunBrk
From Anywhere
Hold
for
”Resync”
Start
”Resync”
Resync=1
Release
min mask
Runo=
(Get
1st
Zc)
ResetunBrk= utEna=oZc
NoZ
Auto/Ext=0
Stuck
Rotor
(hold)et2ndZ) cRet=
OutEna=1
RunBrk=1
StrRtr=0
StrRtr=0
Mono
RunBrk=0
OutEna=0
Figure4: StateDiagram
L6238
2.0 STATE DIAGRAMS
2.1 State Diagram
Figure4isa complete State Diagramof the con-
troller depicting the operational flowasa function the control pins and motor status. The flow can separatedinto four distinct operations.
2.2 Align+ Go
Figure5 represent the normal flow that will
achievea spin-up and phase lockof the spindle
motor. Upon power up, the controller first checks determineif the motoris still spinning. This
”Hold For Resync” decision block will be dis-
cussed later.
Hold& wait
for decision
RunBrk=0
RunBrk=1
Hold for
”Align& Go”
Hold
for
”Resync”
Start
”Align& Go”
Align= Seqncr.
Run
[Align
Phase
[Align
to
Phaselign=0o=0
Power
on
Reset
Align
RunBrk
OutEna
OutEna
RunBrk=1
OutEna=0
OutEna=0
RunBrk=0
Figure5: Align+Go
L6238
Assuming the motoris stationary, with Output
Enable high and Run/Brake low, the controlleris the ”Hold for Align& GO” state. When
Run/Brakeis brought high, the motorisin align
mode with Phase1 active (OutputA high and
OutputB low). Alignisa zero. After the align
time-out (user-programmable), the Alignbit goes
high and the sequencer double increments the
outputsto Phase3 (OutputB high and OutputC
low). After the next time-out, the controller enters
the Go mode, with the sequencer automatically
incrementing the output phase upon detectionof
the motor’s Bemf.
Never commandan Align& Go unlessa refer-
ence signalis presentat PLL FREF, since this the signal that determinesthe lengthof time
that phase1 remains active. Run/Brakeis brought low, (orif the 5V supply removed) the controller will revertto ”Hold for
Align& GO” and the serial port will be reinitial-
ized.In orderto preventan erroneous restart con-
dition,itis necessary that Run/Brakebe held low
until the motor has completely stopped. Once the
motor has stopped, Run/Brake may be brought
highfora completeAlign& Go Start-Up routine.
2.3 Resynchronization poweris momentarily lost, the sequencer can
automatically resynchronize to the monitored
Bemf. This resychronization can either occur
whenever Output Enableis first brought low then
highorif the Logic Supplyis momentarilylost.
Referringto figure6, the ”Hold for Resync” state entered upon POR (Power On Reset)or when-
ever Output Enableis brought low. The control-
ler leaves this state and enters ”Start Resync”
when Output Enableis high. zero crossings are detected, the sequencer will
automatically lock onto the proper phase and
bring the motor speedupto Phase Lock.
This resynchronization will take effect with the
motor speed runningas low as typically 30%of
it’s nominal value.
Never command an Align& Go while the mo-
toris spinning. Always initiatea resync first initiate brake mode and allow the motorto
spin down.
Power
on
Reset
Hold
for
”Resync”
Start
”Resync”
Resync=1
Release
min mask
Run
OutEna=1
(Get
2nd
Zc)
Reset
(Get
1st
Zc)
Reset
RunBrk=1 utEna=0oZc
NoZ
Figure6: Resync.
L6238
2.4 Stuck Rotor/Monotonicity
Referto figure7.In orderto alert the microproc-
essorof fault conditions, two bits are availablein
the Serial Port’s Status Register. Stuck Rotor the controller enters the Go mode after the Dou-
ble Align, Bemf must be detected within 419ms
when usinga system clock frequencyof 10MHz. this conditionis not met, the outputs will be tris-
tated and set thisbittoa zero. The controller en-
ters the ”Stuck Rotor Hold” state. Mono
When the motor spins up normally, the resultantP IN SENSE pulses risein frequencyina
monotonic pattern. Any fault condition that would
causea rapid decreasein the SPIN SENSE fre-
quency would be detected by internal counters
setting the MONO bit low and forcinga Brake
condition
2.5 External Sequencing
Although the user-defined Start-Up Algorithmis
flexible and will consistently spinupa motor with
minimum external interaction, the possibility ex-
ists where certain applications might require com-
plete microprocessor controlof start-up.
The L6238 offers this capability via the SE-
QUENCE INCREMENT input. Referringto figure with Output Enable and Run/Brake low, the
controllerisin the ”Hold and Wait for Decision”
state.If the SEQUENCE INCREMENT pinis
brought high during this state, the Auto StartUp
Algorithmis disabled and the sequencer can be
controlled externally.
When Output Enable and Run/Brake are
brought high, the sequenceris incremented every
time that the SEQUENCER INCREMENT pinis
first brought low and then high. During the time
that this pinis high, all Bemf informationis
Run
Stuck
Rotor
(hold)
OutEna=1
RunBrk=1
Mono
StkRtr
Figure7: Stuck Rotor/Monotonicity.
Brake
W/Mask
Hold& wait
for decision
Tri-state
W/Mask
Tri-state
W/Mask
RunBrk=1
OutEna=0
RunBrk=1
OutEna=1
OutEna=1
Run
W/Mask
RunBrk
OutEna
Power
on
Reset
OutEna
RunBrk
RunBrk
RunBrk=0
OutEna=0
SeqInc=X
Hold
for
”Resync”
RunBrk1 utEna0
Run
Wo/Mask
SeqInc=0
SeqInc=1
SeqInc=0
SeqInc=1
Action across
line increments
sequencer
Auto Start-up
Enabled Disabled
RunBrk=1
OutEna=0
RunBrk=1
OutEna=1
OutEna=0
RunBrk=0
Figure8: Ext. Sequence.
L6238
masked out, and whenitis low, the Bemf informa-
tion can be detected normally. When the motor
has reacheda predetermined speed, the SE-
QUENCE INCREMENT pin can be left low and
the L6238 Motor Control logic will take over and
automatically bring the motor into Phase Lock.
3,0 START-UP ALGORITHMS
3.1 Spin-Up Operation
The spin operation canbe separated into3 parts: Open Loop Start-Up- The objectisto create
motionin the desired directionso that the Bemf
voltagesat the3 motor terminals can provide reli-
able information enablinga transitionto closed
loop operation. Closed Loop Start-Up- The Bemf voltage
zerocrossings provide timing informationso that
the motor can be acceleratedto steady state
speed. Steady-State Operation- The Bemf voltage
zero-crossings provide timing informationfor pre-
cision speed control.
The L6238 contains features that offer flexible
control over the start-up procedure. Either the on-
board Auto-Start Algorithm canbe usedto control
the start-up sequenceor more sophisticated exte-
mal start-up algorithms can be developed using
the Serial Port and key control/sense functions
brought outto pins.
3.2 Auto-Start Algorithm
The Serial Port ControlBit Auto/Ext (Referto Ta-
ble 2), controls the start-up mode. The powerup
default stateisa logic high which selects the
AutoStart Mode. When Run/Brakeis low, the
L6238isin brake mode, and the Auto-Start Algo-
rithmis reset.In the brake mode,allof the lower
DMOS drivers are ON, and the upper drivers are
OFF.
Note that Run/Brake shouldbe brought low fora
period exceeding the value selectedfor the brake
delay timein orderto initialize the brake delay cir-
cuit.
The Auto-Start Algorithmis based on an Align& approach and canbe visualizedby referringto
Figure9. Shown are the Output Enable and
Run/Brake control signals, sequenceroutput with
the resultant output phases, and the Align and Go
status bits. The times labeledTl and T2 are two
Figure9: Auto Start Profile
Tasd <1> Tasd <0> Ta =T1 T2 Tg
0.178s
0.356s
0.533s
0.533s
1.067s
1.600s
0.711s
1.422s
2.133s
L6238
delays that are 25% and 7S% respectivelyof the
total delay selectedby the Auto-Start Delay Con-
trol Bits. The times labled T1 andT2 are the times
associated wim the Align and Go status bits. Typi-
cal delays associated with these times fora PLL
reference frequencyof 90Hz are shownin the fig-
ure.
Referringto figure9, the followingis the se-
quenceof events during Auto-Start:
Alignment Phase Output Stageis energizedto phase1 with
OUTPUTA high and OUTPUTB low forT
seconds. The intemal sequencer double increments the
output stageto Phase3 for T2 seconds.If
phases1or3 are high torque states, the mo-
tor should become aligned. During the alignment phase, the SEQ INCRE-
MENT signalis ignored. Phase The internal sequencer double increments the
output stageto State5, which should produce
torquein the desired direction. with SEQ INCREMENT held low, the se-
quenceris now controlledby the Bemf zero
crossings, and the motor should ramp upto
speed. backward rotationis detected,a statusbitin the
serial port willbe set, and the L6238 will revertto
the brake mode.Ifa stuck rotor condition exists, the Stuck Ro-
tor Status bitis flagged, but no actionis
taken.If though duringa stuck rotor condition,
the time out dueto the backwardsrotation oc-
curs, the L6238 will revert backto the brake
mode.
3.3 Externally Controlled Start-Up Algorithms
Enhanced Start-Up Algorithms can be achieved usinga uProcessorto interact with the L6238’s
control and status signals. The uProcessor needsbe heavily involved during OpenLoop Start-Up.
The L6238 has the abilityto transitionto Closed
Loop Start-Upat very low speeds, reducing the
uProcessor taskto monitoring status rather than
real time interaction. Thus,itisa perfect applica-
tionforan existinguProcessor. allow control via an external means, the
Auto/Ext ControlBitin the Serial Port mustbe set
low. This disables the internal Auto-Start Algo-
rithm. The following control and status signalsal-
lowfor very flexible algorithm development:
SEQ_INCRA lowto high transitionat this input usedto increment the stateof the power out- cycle through the statesat any desired rate.
When held high,it inhibits the BEMF zero
crossings from incrementing the internal se-
quencer.
SPIN SENSE This outputis low until the first
detected Bemf zero crossing occurs.It then
togglesat each successive zero crossing. This
signal serves asa motion detector and gives
useful timing informationas well.
LOCKA high denotes that the phase error be-
tween the PLL reference and the feedbacksig-
nalsis within the programmed threshold. This
signalis updated once per revolution.
Seq Reset Thisbitis usedto reset the output
stageto the first state.
3.4 Start Up Approaches
Align& Go Approach The Align& Go approach
providesa very time efficient algorithmby ener-
gizing the coilsto align the rotor and statortoa
known phase. This approach canbe achieved via
the Seq Reset,or by sequencing SEQ INCR.
SPIN SENSE can be monitoredto assure that
motion occurred. Once ample timeis given for
alignmentto occur, SEQ INCR canbe doublein-
cremented, and the SPIN SENSE pin can be
monitoredto detect motion. When SEQ INCRis
pulled low, controlis transferredto the internal se-
quencer, and the L6238 finishes the spinup op-
eration.If no motionis detected, SEQ INCR can incrementedtoa different phase and the proc-
ess can be repeated. The alignment phase may
cause backward rotation, which on the average
willbe greater than the StepperMotor approach.
The Auto-Start algorithm described earlieris an
Align& Go approach. The main advantagesof
the integrated Auto-Start are that the uPis notin-
volved real-time, and there area minimumof in-
terface pins requiredto the spindle control sys-
tem.
Stepper Motor Approach This approach mini-
mizes backward rotation by sequencing SEQ
INCRat an initial rate that the rotor can follow.
Thus,itis drivenina similar fashiontoa stepper
motor. The rateis continuallyincreased until the
Bemf voltageis large enoughto reliably use the
zero-crossings for commutation timing. SEQ
INCRis held low, causing controlto be passedto
the L6238’s internal sequencerasin the Align& approach.
L6238
mustbe low enoughso that the motor can follow
without slipping. This implies thatto havea reli-
able algorithm, the initial frequency and ramp rate
must be chosen for the worst case motor under
worst case conditions.
4.0 DIGITAL PLL MOTOR SPEED CONTROL
4.1 Phase Detector
The internal Phase/Frequency Detectorof the
PLL has two inputs: reference input (Fref) feedback input (Fmtr)
The feedback Inputis multiplexed between thein-
Shownin figure10is the classical state diagram
fora phase detector along with waveform exam-
ples.
Positive phaseis definedas when the reference
falling edge occurs before the falling edgeof
Fmotor and the motor speed mustbe increased.
Negative phaseis just the opposite, requiringa
slowingof the motor speed. an example, the top four waveformsin figure representa positive phase condition.In this
case the ”up” signal wouldgo low since the refer-
ence signal went low before the appearanceofa
negative transitionof fmotor. The falling edgeof
fmotor causes the ”up” signalto revert backtoa
Figure 10: PhaseDetector State Diagram.
L6238
4.2 Counter Section
Figure11isa block diagramof the counter sec-
tionof the PLL along with the phase detector.
The phase detector providesup and down signals
that are usedto control the direction and counting
periodof two8 bit counters. Two counters are
usedto provide both coarse and fine phase error
information. The coarse counter operatesto bring
the phase error intoa finite window, while the fine
counter with it’s higher resolution controls the
phase jitterto typically5μs.an example, duringa positive phase measure-
ment, the counters are resetto 10000000 which the middleof their measurement range corre-
spondingto zero degrees phase error. The falling
edgeof Fref,in conjunction with the ”up” signal,
causes the fine counterto then start counting up.
The coarse counteris inhibitedby the fine counter
until the fine counter has reached it’s maximum
count. The falling edgeof Fmtr causes the count-
ersto stop counting and the bitsin the fine and
course counters are then latched into their re-
spective latches. The counters are then resetto
10000000in anticipationof the next phase meas-
urement.
The operationof the counter section during spin- and phase lock can be describedin three
entlybring the motor speed”in line” with the refer-
ence frequency.The phase detectoris initialized power upto force the countersto start counting
up.
Since there will be many more Fref.vs Fmtr fall-
ing edgesat start-up, the widthof the ”up” pulse
willbe wide. The fine counter will reach it’s maxi-
mum count and send an enable pulseto the
coarse counter causingitto start counting. After
127 counts, the coarse counter also reaches it’s
maximum count.At the endof the ”up” pulse, it’s
rising edge loads the outputsof the Coarse and
Fine counters into corresponding latches. Thus
the latches are updated once-per-rev witha bi-
nary number that correspondsto the measured
phase error. This count will be converted viaa
Digitalto Analog Convertors (DAC) intoa speed
Command Voltage, whichat start-up will be the
maximumas setby the ILIM SET voltage. Overshoot- As the motor speed increases
closeto the reference, the coarse counter comes
outof compliance and decreasesit’s countas the
phase difference becomes smaller. The fine
counter then takes over when the phaseisina
certain range.A certain amountof phase over-
shoot will take placeas the motor passes though
zero phase difference dueto the closed loop sys-
tem response characteristics.
Figure 11: Logic Block Diagram.
L6238
Phase Lock- Aftera brief settling time, typi-cally 1-2 seconds after spin-up, the counters will
alternately count up and down as requiredto
maintain the phase differenceto be as closeto
minimumas possible. The counter outputsat this
time shouldbe ”hovering” around 10000000.
The outputsof the two DACs are sentto latches
that store the digital representationof the meas-
ured phase error. This informationis then bussed the DACs.
4.3 Coarse/FineDACs
Two DACs are usedto convert the digital phase
error information intoan analog voltage that can usedto command the output driver’s current. figure 12, the two 8-bit digital error signals are
usedto switchin 256 possible voltages derived
froma precision Band-Gap reference. The same
resistor ladder stringis used for the Coarse and
Fine DACs. The outputsof the DACS are then
sentto buffer stages and added together viaa
summing amplifier.
4.4 Transfer Functions
Figure13 represent the Output Voltagevs Phase
Error for the Coarse and Fine DACs depicting the
resolution thatis achievable.
Table2 shows examplesof the resolutionof both
Figure 12: Coarseand Fine DAC’s.
Table2
Fsystem
Clock Fcoarse Phase LSB
Coarse
(Range)
Coarse Ffine Phase LSB
Fine
(Range)
Fine
8MHz 15.6KHz 64.1μs 16.3ms 1.0MHz 1.0μs 255μs
L6238
DACsasa functionof the system clock repetition
rate. Fcoarseis the system clock dividedby 512,
while Ffine divides the clockby8. This gives for
example, Coarse and Fine LSB’sof 51.3us and
800ns respectively fora system clock repetition
rateof 10MHz. Therefore the best phase jitter that
could be achieved asa functionof the counter
resolutionis 800ns. The dynamic rangeof each
counteris also shownin the table. can be seen that the ratioof Fineto Coarse
countsis 64. The summing amplifler divides the
Fine DAC buffer output voltagebya factorof 16.
Therefore thereisa 4:1 ratioof Fineto Coarse
gain.
This resultsina Speed Control Loop thatis fairly
easyto compensate with excellent transient re-
sponse.
The outputof the PLL Detectoris fedtoa gener- purpose. filter amplifier thatis usedto compen-
sate the Speed Control Loop. The filter amplifier
output stage has been carefully designedto limit
the compliance voltagetoa value that tracks the
Ilim Set voltage, thus limiting the amountof over-
shoot and enhancing the transient responseof
the loop.
OUTPUT voltage asa functionof the detected
phase differenceas measuredon production ma-
terial. The changeof the gain slopeis apparent
around the zero phase difference point. With the
spindle motor at phase lock, the DETECTOR
OUTPUT voltageis typically 2.0, equivalentto the
internal Virtual Ground level.
Figure 13: Coarse/Fine DAC’s Output Graphs.
Figure 14: Vdetector Outputvs Phase Error.
L6238
5.O MOTOR DRIVER
5.1 Output Stage
The output stage formsa 3-phase, full wave
bridge consistingof six Power DMOS FETs capa-
bleof 2.5 amps. Higher output currents are al-
lowed for brief periods. Output Power exceeding
the stand-alone power dissipation capabilitiesof
the L6238 can be increased with the additionof external P-FET.
Table3isa reference diagram that lists the pa-
rameters associated with 8-pole motors operating 3600 and 5400 RPM.
Figure 15 represents the waveforms associated
with the output stage. The upper portionof fig-
ure 15 shows the flowof currentin the motor
windings for eachof the24 phase increments.A
rotational degree indexis shownasa reference
along witha base lineto indicate the occurrencea zero crossing. The3 output waveforms are
actual digitally reproduced voltage signals as
measuredon samples. typical sequence starts when the outputsswitch
states. Referringto figure 15, during phase1, out-
putA goes high, while outputBis low. During this
phase, outputCis floating, and the Bemfis moni-
tored. The outputs remainin this state for60 elec-
trical degrees as indicated by the first setof
dashed lines. After this period the output switches phase2 with outputA high andC low with the
Bemf amplifier monitoring outputB. orderto prevent commutation current noise be-
ing detectedasa false zero crossing,a masking
circuit automatically blanks outall incoming sig-
nals as soon asa zero crossingis detected.
When the next commutation occurs an internal
counter starts counting downto set the time that
the masking pulse remains The counteris initially
loaded witha number thatis equalto period that always 25%of the previousphase periodor15
electrical degrees. This time-outof the masking
pulse shownfor referenceat the bottomof figure
16. Thus the actual masking periodis the totalof
the time from the detected zero crossingto the
commutation, plus 25%of the previous period.
The mask pulse operationis further discussedin
section 5.6, Slew Rate Control.
After the masking period, the Bemf voltageat out-
putBis monitored fora zero crossing. Upon de-
tectionof the crossing the outputis sequencedaf-
ter 30 electrical degrees insuring maximum
Table3.
Rotational Speed 3600 rpm 5400 rpm
Rotational Freq. 60Hz 90Hz
Rotational Period 16.667ms 11.111ms
Electrical Period 4.167ms 2.778 ms
Phase Period 694.5μs 463.0μs
L6238

Partno	Mfg	Dc	Qty	Available	Descript
L6238	STM	N/a	5	avai	SENSORLESS SPINDLE MOTOR CONTROLLER