L6234 ,THREE PHASE MOTOR DRIVERThermal Characteristics of the PowerDipshown, is created making use of the printed cir-20,24 Packag ..
L6234PD ,THREE PHASE MOTOR DRIVERL6234THREE PHASE MOTOR DRIVERSUPPLY VOLTAGE FROM 7 TO 52V5A PEAK CURRENTR 0.3Ω TYP. VALUE AT 25°C D ..
L6234PD ,THREE PHASE MOTOR DRIVERTHERMAL CHARACTERISTICSthermal connection with the external world (veryRth j-pinsthin strips only) ..
L6234PD013TR ,THREE PHASE MOTOR DRIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Power Supply Voltage 52 VSV ,V Input Enable Vo ..
L6235D ,THREE PHASE BRUSHLESS DC MOTOR DRIVERABSOLUTE MAXIMUM RATINGSSymbol Parameter Test conditions Value UnitV Supply Voltage V = V = V 60 VS ..
L6235N ,THREE PHASE BRUSHLESS DC MOTOR DRIVERBLOCK DIAGRAMV VSBOOTAVBOOT VBOOTCHARGE THERMALVCPPUMP PROTECTIONOCD1OUT1DIAGOCD1 10VOCD OCD2OCD3OC ..
LC32464M-80 ,256K (65536 words X 4 bits) DRAM Fast Page ModeFeatures. 65536 words K 4 bits configuration.. RAS access time/cycle time/power dissipation256 K (6 ..
LC32464P-80 ,256K (65536 words x 4 bit) DRAM fast page modeBlock DiagramR A S o---- Clock generator No,1 ___-__- (w --C) v C CCAS Cy- 9., Clock generalorNo. 2 ..
LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC331632M-70 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..
LC338128M-70 ,1 MEG (131072 words x 8 bit) pseudo-SRAMFeatures. 131072 words x 8 bits configuration. CE access time, COE access time, cycle time, operati ..
LC338128M-80 ,1 MEG (131072 words x 8 bit) pseudo-SRAMPin AssignmentAuA1:A7A5"A:"A2Al"1/0:1/021/0:END 1DIP32, SOP32VccA15Ax:1/051/07TADSvns1/04Top viewAu ..
L6232E
SPINDLE DRIVER
L6232ESPINDLE DRIVER
1.5A MAXIMUM PEAK CURRENT
CONTROLLED SLEW RATE
CENTRAL CHARGE PUMP
PWM AND LINEAR MODES
CUTOFF TIME USER CONFIGURABLE
FAST, FREE-WHEELING DIODES ON CHIP
OVER-TEMPERATUREPROTECTION
BRAKE FUNCTION INPUT
DESCRIPTIONThe L6232Eisa triple half bridge driver intended
for usein brushless DC motor applications. This
part can be usedto form the power stageofa
three-phase, brushless DC motor control loop,
andis especially useful for disk drive applications.
Power drivers are Integrated DMOS transistors
and feature fast recirculating diodesasan integral
partof their structure. The logic inputs are TTL-
level compatible, with internal pull-up, allowingin-
terfacingto open collector outputs. All necessary
circuitryto perform PWM and linear motor speed
controlis included.A central charge pumpis util-
izedto drive the upper DMOS transistors, and
alsoto power the braking function. The L6232Eis
packagedin PLCC28.
October 1996
BLOCK DIAGRAM
PLCC21+7
ORDERING NUMBER: L6232E
1/10
PIN CONNECTION (Top view)
PIN DESCRIPTION
Pin Name Functionto4 GND Common Ground. Also provides heat-sinkto PCB.9 SENSE Outputfor current sense resistors. INLB Logic Inputto turnon the lower driver(Active High).11 VS Supply Voltage. INLA Logic inputto turnonthe lowey driver (Active High). CS External Charge Pump Capacitor. CP External Main Charge Pump capacitor. RC Cutoff Time RC Networkin PWM mode. The Resistor valueis also usedto define
the slew-ratein linearmode (LIN). INLC Logic inputto turnonthe lower driver (Active High). BRK DLY External RC networkforthe brake delay. INUC Logic Inputto turnon the upper driver (Active Low). PWM Vref Inputfor Reference Controlin PWM mode LIN Vref Inputfor Reference Control voltagein LIN mode COMP External compensationfor error amplifier OUTA DMOS Half-bridgeA Out. BRK Active LOW logic input that triggersthe delayed brake. OUTB DMOS Half-bridgeB Out. INUA Logic Inputto turnon the upper drivers (Active Low). INUB Logic Inputto turnon the upper drivers (Active Low). OUTC DMOS Half-bridgeC Out.to28 GND Common Ground. Also provides heat-sinkto PCB.
L6232E2/10
THERMAL DATA
Symbol Description Value UnitRthj-pin
Rth j-amb
Thermal Resistance Junction-pins
Thermal Resistance Junction-ambient (**)
Max.
Max.
°C/W
°C/W
Notes(*) Pulse width (limited onlyby junctiontemperature andbythe transient thermalresistance.
(**) Mountedon board with 16cm2 35μm thickness copper areaon board heatsink.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVDSsus Peak Output Sustaining Voltage 15 V Supply Voltage 15 V
VOpeak Output Peak Voltage (tpK=5 μsec; 10% d.c.) 18 V
VCp Charge Pump Input Voltage 30 V Logic Input Voltage -0.3to7 V
VREF PWM VREF--LIN VREF Input Voltage -0.3to7 V
Vis Sense Input Voltage -1to7 V Sink-Source Peak Output Current(*) 3.5 A Sink-Source DC Output Current 1.8 A
Ptot Total Power Dissipation (Tamb =70°C) 1.5 W
Tstg,Tj Storage and Junction Temperature -40to 150 °C
ELECTRICAL CHARACTERISTICS (See the block diagram,VS =12V,R= 100KΩ;C= 180pF; =25°C, unless otherwise specified)
Symbol Parameter Test Condition Min. Typ. Max. Unit Supply Voltage 10.5 12 13.5 V Quiescent Supply Current BRK=L; INUA= INUB= INUCL; INLA= INLB= INLC=H;
Table1
0.3 0.5 mA
BRK=H; INUA= INUB= INUCH; INLA= INLB= INLC=L;
Table1 mA
IOL Output Leakage Current VO =VS= 13.5V 1 mA
RDSon Sink Out ON Resistance Tj =25°C (see Fig.4) 0.42 0.47 Ω= 125°C 0.7 Ω
RDSon Source Out ON Resistance Tj =25°C (see Fig.4) 0.42 0.47 Ω= 125°C 0.7 Ω Body Diode Forward Drop (sink
and source)
IDS=1A (see Fig.6) 1 1.5 V
td(BRK) Brake Delay Time See Fig.1,3; note1 210 ms
TBRK Braking Time 10 s
IB(LIN) LIN Vref Input Bias Current LIN Vref= 0.4to 5.5V 400 950 nA
IB(PWM) PWM Vref Input Bias Current PWM Vref= 0.4to 5.5V 400 950 nA
LIN Vref Reference Voltage Input Note2;RS= 0.5Ω
Imotor (PWM)=1A
Imotor (LIN)= 200mA
PWM Vref 0.4 V Sense Amplifier Voltage Gain PWM Vref= 2.5V,
LIN Vref= 0.4V,= 0.5Ω; Note2
3.7 4 4.3 V/V
L6232E3/10
Symbol Parameter Test Condition Min. Typ. Max. Unit LIN Error Amplifier
Transconductance
0.8 mA/V
Zout Error Amplifier Output
Impedance
2MΩ
VINH Logic Input Voltage BRK; INUA;
INUB; INUC; INLA; INLB; INLC
VINL 0.8 V
IINH(leak) Logic Input Current BRK;INUA;
INUB; INUC; INLA; INLB; INLC= 2.7V -1 mA
IINL Vi= 0.4V -0.1 mA
tdonU Upper/Lower Turn-on Delay Table1 see Fig.3 0.7 μs
tdonL 0.15 μs
tdoffU Upper/Lower Turn-off Delay 15 μs
tdoffL 0.5 μs
dV/dt Source DMOS Slew-Rate
(PWM)
see Fig.3 10 V/μs
dV/dt Source DMOS Slew-Rate (LIN) see Fig.3 1 V/μs
dV/dt Sink DMOS Output Turn-off
Slew-Rate
Note3;R= 100KΩ 0.15 V/μs Internal Clock Frequency 380 KHz
Toff PWM Cutoff Time R=100KΩ; C=180pF, Note4;
see Fig.2 μs
Tsd Shutdown Temperature 160 °C
Tsdr Recovery Temperature 120 °C
Notes: The HeadPark timemustbe shorter thanthe Brake Delay timetd(BRK) =RdCd Bothin PWMandin LINmode theRef. Voltagemust agreetoVref=GVRS Imotor The resistanceoftheRC network definesthe dv/dt value.toff= 1.8RC+6⋅10-6
ELECTRICAL CHARACTERISTICS (continued)
Table1
INPUT STATE OUTPUT STATE
INUA INUB INUC INLA INLB INLC A B CLLL H H H* * *
LLL LL L H H H
HHH L L L * * *
HHH HH H L L L= The Upper DMOSisON= The Lower DMOSisON= Tristatecondition
L6232E4/10
FUNCTIONAL DESCRIPTION (Refer to the
Block Diagram)
The commutation sequenceis provided by the
user via six inputs. INUA,INUB,INUC turnon the
three upper DMOS drivers when heldat logic
LOW, and inputs INLA,INLB,INLC turn on the
three lower DMOS drivers when held at logic
HIGH.
The BRK and BRK DLY inputs offer flexibilityto
the system designerin the implementationof the
braking function. The BRK logic input, when
pulled low will turn-offall upper and lower Dmos
drivers. The low transitionat BRK will producea
delayed negative transitionat the BRK DLY input,
configurableby connectionofa capacitor Cd and resistor Rd from the BRK DLY pinto ground.
The negative transitionat BRK DLY will initiate
the brakingof the motorby turning on all lower
Dmos, while keepingall upper DMOS turned-off.
This feature providesa time interval where the
motor BEMF can be usedto power the head
parking function before the braking procedureis
iniziated. External detection of the supply(VP)
drop-offis necessaryto provide the appropriate
logic signalto the BRK input. (see Fig.1)
The brake function utilizes the energy storedin
the central charge pump capacitor (Cp)to turn-on turn-off the DMOS drivers. This allows for
completionof the braking procedure after the VP
supply has powered down.
The L6232Eis capableof driving the motorin
either pulse width modulation (PWM)or linear
(LIN) mode. The driving modeis determinedby
the smallerof two analog voltages inputs, LIN
Vref and PWM Vref. The motor currentis control-
led by LIN Vref and PWM Vref and the current
sense resistor Rs connectedto the SENSE out-
put. The SENSE output providesfor connectionof resistorin series with the sourceof all lower
DMOS drivers. The voltageat this pin provides
the error signal wichis utilized internallyto regu-
late the motor current Im. The currentin both
PWM and linear modeis determinedby the ex-
pression:= Vref⋅ RS wich Gvis the voltage gainof the sense ampli-
fier.In linear mode, the currentis regulatedbya
linear control loop wich drives the lower DMOS.
Compensation of the linear control loop is
achieved by connectionofa series network
(Rc,Cc) from the transconductance amplifier out-
put (Gm) and ground. Controlis passedto each
lower DMOSin succession during the commuta-
tion sequence(MPX).
The rateat which the upper and lower drivers
turns-off during linear mode operationis configur-
able externallyby the valueof the resistorR used the RC pin. This definesa current whichis util-
ized internallyto limit the voltage slew-rateat the
outputs during transitions. The output slew-rateis
internally adjusted for fast slewing during PWM
operation to reduce losses, anda relatively
slower rate during linear mode operationto mini-
Figure1: Brake Delay and Braking timingof the L6232E.At the timet1a VP Powerdownthreshold
detectordrives low the BRK input;at timet2 the Charge Pump voltage becomes inadequate maintain ON the lower DMOS.
L6232E5/10
mize noise effects(EMI). LIN Vref and PWM Vref
are connected toa comparator whose outputis
fedto the logic. The upper and lower DMOS
driver slew-rates are controlled by the internal
logic. PWM mode, the upper driveris turned-off when
the motor current reaches the intended value. An
internal One-Shot pulse determines the lenghtof
time the upper driver stays off before turning on
again. The pulse width, and thus the cutoff time
(toff),is configurableby meansof the external RC
network connectedto the RC pin. (see Fig. 2). The
resistorat the RC pin, therefore determines both
the driver output slew-rate during linear mode and
the off-time constant during PWM. The lower driver always on during PWM modeof operation;an
on-chip 2μs mask can prevent the beginningofa
new cutoff time becauseof transient current spikes
causedby theupper drivers turn-on.
The driving modeis determinedby the smallerof
the two controlling input voltages.Ina typical ap-
plication the motor start-up would occurin PWM
modeto limit power dissipation, with on-speed
control then performedin linear mode.
Thermal protection circuitry will shut-offall drivers
when the chip junction temperature exceeds the
threshold temperature.A small amountof hyster-
esisis includedto prevent rapid on/off cyclingof
the power stages.
Additionalprotectionis provided against driver input
combinations where the upper and lower driversof half bridge are turnedon simultaneusly, resultinga short from supplyto ground.The chip logic will
cause both the upperand lower drivers involvedto
turn-off. (see Table1)
APPLICATION INFORMATION typical application configurationof the L6232E
drivinga three-phase brushless DC motoris
shownin Fig.3. The spindle motorisa4 ohm-
2mH per phase, star connected. This load re-
quiresa suitable compensationof the linear con-
trol loop that can be achievedby Rc= 10 Kohm
and Cc= 10nF (R3;C8). Changing the motor char-
acteristics, the RcCc network would be modified
for the best performancesof the system.At the
start-up the spindleis drivenin PWM mode fixed
toff time.
The off-timeis calculatedby the formula:
toff= 0.69 R2 C7
See fig.2fora quick choiceof the needed capaci-
tor, after the resistor has been fixed. The valueof
the resistor defines the rateat which the upper
and lower drivers turn-off during linear mode op-
erationto avoid EMI effects. During turn-off, the
slew rateis constant for the sink stage, whileit
hasa varying slopefor the source stage because the non linear changeof the gateto source im-
pedanceof the DMOS transistor. Practically, the
slowest slew rateis obtainedat the sink transistor
switch-off time (see fig. 5), thenit increases dur-
ing the first periodof the source transistor switch-
off (source,1st) andit becomes the fastest during
the final portionof the turn-off duration (source,
2nd). The PWMto linear modeof operationis
switchedby decreasing the LIN Vref level under
the PWM Vref value that couldbe fixed and cal-
culated by:
PWM Vref=4 RsIp
whereIpis the peak chopping currentin the mo-
tor windings.Of course, when the required RPM reached,it becomeof no needa strong torque
and the LIN Vref starting froma value higher than
the calculated PWM Vref, decreasesto the value
LIN Vref=4 RsIm
where Im, smaller thanIp,is the neededmotor cur-
rentto keep constant spin. This last reference volt-
ageis generallya PLL output driven by speed
transducers coupledto the spindle (like Hall effect
sensorsor BEMF processors).To drive the upper
DMOS and during the brake functiona voltage
higher than the supply Vsis needed. The charge
pump integratedin the L6232E keeps C3at the
correct voltage. To guarantee efficient brakingof
the motor, C3 mustbe chosenof adeguate quality
(very high equivalent parallel resistance). C4 cana ceramic disk capacitor. The typical applica-
tion od the L6232Eisin HDD systems on which
thereis the needto park the Read-Write Heads be-
fore the motor braking. This behavioris possible
with the circuitof Fig.3.At Power Supply switch-off
(see Fig. 1), VP falls down and drives down the
BRK input (Active Low). D1 insulates the L6232E
from the power suppy output while the power out-
put stageis switchedina high impedance state.
The spindle motor actingasa three-phase alterna-
tor supplies the Heads voice coil motor driven
through integrateddiodes that rectifie the EMF. Af-
tera delay longer than the parking time, the lower
output DMOS are switched-on and the spindlemo-
toris braked. The brake delay timeis tipically 150
msec anditis definedby:
Figure2: Typicaltoff vs. CapacityofC
L6232E6/10
