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L6230STN/a20avaiPowerSPIN: DMOS driver for three-phase brushless DC motor


L6230 ,PowerSPIN: DMOS driver for three-phase brushless DC motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A RMS)■ R 0.73 Ω ..
L6232B ,SPINDLE DRIVERBLOCK DIAGRAM ADVANCE DATA PLC621+7 ORDERING NUMBER: L6232B part of their structure. The ..
L6232E ,SPINDLE DRIVERELECTRICAL CHARACTERISTICS (continued)Symbol Parameter Test Condition Min. Typ. Max. UnitG LIN Erro ..
L6234 ,THREE PHASE MOTOR DRIVERThermal Characteristics of the PowerDipshown, is created making use of the printed cir-20,24 Packag ..
L6234PD ,THREE PHASE MOTOR DRIVERL6234THREE PHASE MOTOR DRIVERSUPPLY VOLTAGE FROM 7 TO 52V5A PEAK CURRENTR 0.3Ω TYP. VALUE AT 25°C D ..
L6234PD ,THREE PHASE MOTOR DRIVERTHERMAL CHARACTERISTICSthermal connection with the external world (veryRth j-pinsthin strips only) ..
LC322260J-70 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writePin assignment conforms to the JEDEC standards for4M DRAM (262144 words x 16 bits, 2C-AsnCrgtype). ..
LC322260J-80 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writeAbsolute Maximum RatingsParameter Symbol Ratings Unit NoteMaximum supply voltage Vcc max -IOto +7.0 ..
LC322271M-80 ,2MEG (131072words x 16bit) DRAM fast page mode, byte writeElectrical Characteristics at Ta = 0 to +70°C, V = 5 V ± 10%CCLC322271J, M, TParameter Symbol Condi ..
LC32464M-80 ,256K (65536 words X 4 bits) DRAM Fast Page ModeFeatures. 65536 words K 4 bits configuration.. RAS access time/cycle time/power dissipation256 K (6 ..
LC32464P-80 ,256K (65536 words x 4 bit) DRAM fast page modeBlock DiagramR A S o---- Clock generator No,1 ___-__- (w --C) v C CCAS Cy- 9., Clock generalorNo. 2 ..
LC331632M-12 ,512K (32768 words X 16 bits) Pseudo-SRAMPin AssignmentLC331632M-70/80l10/12Vcc GNDT TColumnaddressbuffer (7)Row addrebuffer (8)Column decod ..


L6230
PowerSPIN: DMOS driver for three-phase brushless DC motor
June 2011 Doc ID 18094 Rev 2 1/24
L6230

DMOS driver for three-phase brushless DC motor
Features
Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A RMS) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Integrated fast free wheeling diodes Operating frequency up to 100 kHz Non dissipative overcurrent detection and
protection Cross conduction protection Diagnostic output Uncommitted comparator Thermal shutdown Under voltage lockout
Application
BLDC motor driving Sinusoidal / 6-steps driving Field oriented control driving system
Description

The L6230 is a DMOS fully integrated three-
phase motor driver with overcurrent protection,
optimized for FOC application thanks to the
independent current senses.
Realized in BCDmultipower technology, the
device combines isolated DMOS Power
Transistors with CMOS and bipolar circuits on the
same chip.
An uncommitted comparator with open-drain
output is available.
Available in PowerSO36 and VFQFPN-32 5x5
packages the L6230 features a non dissipative
overcurrent protection on the high side power
MOSFETs and thermal shutdown.
Table 1. Device summary
Contents L6230
2/24 Doc ID 18094 Rev 2
Contents Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Field oriented control driving method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 Six-step driving method with current control . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Six-step driving method with BEMF zero crossing detection . . . . . . . . . . 17
6.4 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
L6230 Block diagram
Doc ID 18094 Rev 2 3/24
1 Block diagram
Figure 1. Block diagram
Electrical data L6230
4/24 Doc ID 18094 Rev 2
2 Electrical data
2.1 Absolute maximum ratings
2.2 Recommended operating conditions
Table 2. Absolute maximum ratings
Table 3. Recommended operating conditions
L6230 Electrical data
Doc ID 18094 Rev 2 5/24
2.3 Thermal data
Table 4. Thermal data
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a
thickness of 35 µm). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a
thickness of 35 µm), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat-sinking surface on the board. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
Pin connection L6230
6/24 Doc ID 18094 Rev 2
3 Pin connection
Figure 2. Pin connection PowerSO36 (top view)
Figure 3. Pin connection VFQFPN32 (top view)

Note: The pins 2 to 8 are connected to die PAD.
The die PAD must be connected to GND pin.
L6230 Pin connection
Doc ID 18094 Rev 2 7/24
Table 5. Pin description
Electrical characteristics L6230
8/24 Doc ID 18094 Rev 2
4 Electrical characteristics

(VS = 48 V, TA = 25 °C, unless otherwise specified)
Table 6. Electrical characteristics
L6230 Electrical characteristics
Doc ID 18094 Rev 2 9/24
Figure 4. Switching characteristic definition
Tested at 25 °C in a restricted range and guaranteed by characterization See Figure4. Measured applying a voltage of 1 V to pin CP+ and a voltage drop from 2 V to 0 V to pin CP-. See Figure5.
Table 6. Electrical characteristics (continued)
Electrical characteristics L6230
10/24 Doc ID 18094 Rev 2
Figure 5. Overcurrent detection timing definition
L6230 Circuit description
Doc ID 18094 Rev 2 11/24
5 Circuit description
5.1 Power stages and charge pump

The L6230 integrates a three-phase bridge, which consists of 6 power MOSFETs connected
as shown on the block diagram (see Figure 1), each power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Cross
conduction protection is implemented by using a dead time (tDT = 1 µs typical value) set by
internal timing circuit between the turn off and turn on of two power MOSFETs in one leg of
a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 6. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Table7.
Figure 6. Charge pump circuit
Table 7. Charge pump external component values
Circuit description L6230
12/24 Doc ID 18094 Rev 2
5.2 Logic inputs

Pins INx and ENx are TTL/CMOS and microcontroller compatible logic inputs. The internal
structure is shown in Figure 7. Typical value for turn-on and turn-off thresholds are
respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin DIAG-EN has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 8 or Figure 9. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 8. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN
are connected as shown in Figure 9. The resistor REN should be chosen in the range from
2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and 5.6 nF.
More information on selecting the values is found in the overcurrent protection section.
Figure 7. Logic inputs internal structure
Figure 8. Pin DIAG-EN open collector driving
Figure 9. Pin DIAG-EN push-pull driving
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